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EDBA164B4PR-1DITF-R 数据表(PDF) 135 Page - Micron Technology |
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EDBA164B4PR-1DITF-R 数据表(HTML) 135 Page - Micron Technology |
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135 / 152 page  Table 91: AC Timing (Continued) Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes 1066 933 800 667 533 400 333 Mode Register Parameters MODE REGISTER WRITE command period tMRW MIN 5 5 5 5 5 5 5 5 tCK (avg) MODE REGISTER READ command period tMRR MIN 2 2 2 2 2 2 2 2 tCK (avg) Core Parameters15 READ latency RL MIN 3 8 7 6 5 4 3 3 tCK (avg) WRITE latency WL MIN 1 4 4 3 2 2 1 1 tCK (avg) ACTIVATE-to-ACTIVATE command period tRC MIN – tRAS + tRPab (with all-bank precharge), tRAS + tRPpb (with per-bank precharge) ns 17 CKE minimum pulse width during SELF REFRESH (low pulse width during SELF REFRESH) tCKESR MIN 3 15 15 15 15 15 15 15 ns SELF REFRESH exit to next valid command delay tXSR MIN 2 tRFCab + 10 ns Exit power-down to next valid command delay tXP MIN 2 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns CAS-to-CAS delay tCCD MIN 2 2 2 2 2 2 2 2 tCK (avg) Internal READ to PRECHARGE command delay tRTP MIN 2 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns RAS-to-CAS delay tRCD MIN 3 18 18 18 18 18 18 18 ns Row precharge time (single bank) tRPpb MIN 3 18 18 18 18 18 18 18 ns Row precharge time (all banks) tRPab 4-bank MIN 3 18 181818181818 ns Row precharge time (all banks) tRPab 8-bank MIN 3 21 212121212121 ns Row active time tRAS MIN 3 42 42 42 42 42 42 42 ns MAX – 70 707070707070 μs WRITE recovery time tWR MIN 3 15 151515151515 ns Internal WRITE-to-READ command delay tWTR MIN 2 7.5 7.5 7.5 7.5 7.5 10 10 ns Active bank a to active bank b tRRD MIN 2 10 10 10 10 10 10 10 ns Four-bank activate window tFAW MIN 8 50 505050505060 ns Minimum deep power-down time tDPD MIN – 500 500 500 500 500 500 500 μs Temperature Derating16 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM AC Timing 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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