28HS01GTAM03 datasheet(38/138 Pages) INFINEON

38 / 138 page

Datasheet

38 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.3.2

Program / erase

The program operation is performed when the host specifies a program transaction while CS# is LOW. Up to 256

bytes / 512 bytes can be written (burst writes) to consecutive addresses without issuing a new program trans-

action. The erase operation is performed when the host specifies an erase transaction while CS# is LOW. Either a

single sector or the complete device can be erased.

For transaction protection, the slave device will perform the CRC over the entire instruction sequence (CS# LOW

state) using the proposed CRC32 polynomial. Once the CS# is brought HIGH to complete the Program / Erase

transaction, the CRC calculation will be stopped and the checksum latched into the CRC Register. If multiple

Program / Erase transactions are executed by the host, the slave will continue updating the CRC checksum

between every CS# LOW cycle.

Figure 40

Program CRC Protection

The host device will read the CRC checksum from the slave device using the Read Interface CRC transaction. The

slave device will include the RDCRC_4_0 transaction as part of the CRC checksum and then place the checksum

data on the data bus. If the host device upon receiving the slave’s CRC checksum finds a mismatch with its own

calculated CRC checksum, it can re-issue the Program / Erase transaction to the slave device. For Flash, multiple

Program / Erase to the same location due to CRC checksum errors will affect data endurance. Figure 41 shows

the solution to this issue.

CS#

Command

(16 Bits)

Address

(32 Bits)

Write Data

(n Bits)

DQ[7:0]

Program Transaction

CRC32 - Equation

CRC Read

Every 32-bits of data is shifted into

CRC32 and the Checksum is updated

CS#