28HS01GTAM03 datasheet(57/138 Pages) INFINEON

57 / 138 page

Datasheet

57 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.8.3.2

Read status registers transaction

The Read Status Register (RDSR1_0_0/RDSR1_4_0, RDSR2_0_0/RDSR2_4_0) transactions allow the registers’

volatile contents be read. The SPI mode has no address cycles whereas the Octal mode has four dummy address

of “00h”. The transaction uses latency cycles set by (CFR3V[7:6]) for reading volatile registers to enable maximum

clock frequency of 166MHz under SPI mode, 166MHz under HL-T Octal mode, and 200MHz under HS-T Octal mode

(see Table 49). The Octal mode supports the DS for capture of data (see Transaction table on page 95).

The volatile version of Status Registers contents can be read at any time, even while a program, erase, or write

operation is in progress.

It is possible to read Status Register 1 continuously by providing multiples of eight clock cycles. The status is

updated for each eight cycle read. This is limited to only under SPI mode.

4.8.3.3

Read dynamic protection bit (DYB) access register transaction

The Read DYB Access Register (RDDYB_4_0) transaction reads the contents of the DYB Access Register. The trans-

action uses latency cycles set by (CFR3V[7:6]) for reading volatile registers to enable maximum clock frequency

of 166MHz under SPI mode, 166MHz under HL-T Octal mode, and 200MHz under HS-T Octal mode (see Table 49).

The Octal mode supports the DS for capture of data (see Transaction table on page 95). It is possible to read DYB

Access register continuously, however the address of the DYB register does not increment, so the entire DYB array

cannot be read in this fashion. Each location must be read with a separate Read DYB transaction.

4.8.3.4

Read persistent protection bit (PPB) access register transaction

The Read PPB Access Register (RDPBB_4_0) transaction reads the contents of the PPB Access Register. The trans-

action uses latency cycles set by (CFR2V[3:0]) to enable maximum clock frequency of 166MHz under SPI mode,

166MHz under HL-T Octal mode, and 200MHz under HS-T Octal mode (see Table 49). The Octal mode supports

the DS for capture of data (see Transaction table on page 95). It is possible to read PPB Access Register contin-

uously, however the address of the PPB register does not increment, so the entire PPB array cannot be read in

this fashion. Each location must be read with a separate Read PPB transaction.

4.8.3.5

Read PPB lock registers transaction

The Read PPB Lock Register (RDPLB_0_0, RDPLB_4_0) transactions allow the content of the nonvolatile registers

to be read. The SPI mode has no address cycles, whereas the Octal mode has four required address bytes of “00h”.

The transaction uses latency cycles set by (CFR3V[7:6]) for reading volatile registers to enable maximum clock

frequency of 166MHz under SPI mode, 166MHz under HL-T Octal mode, and 200MHz under HS-T Octal mode. The

Octal mode supports the DS for capture of data (see Transaction table on page 95). It is possible to read PPB

Lock Bit continuously.

4.8.3.6

Read ECC data unit status

The Read ECC Data Unit Status (RDECC_4_0) transaction is used to determine the ECC status of the addressed

unit data. In this transaction, the LSb of the address must be aligned to an ECC data unit. This transaction uses

latency cycles set by (CFR3V[7:6]) for reading volatile registers to enable maximum clock frequency of 166MHz

under SPI mode, 166MHz under HL-T Octal mode, and 200MHz under HS-T Octal mode. The Octal mode supports

the DS for capture of data (see Transaction table on page 95).

The byte contents of the ECC Status for the selected ECC unit is then output. Any following data will be indeter-

minate. To read the next ECC unit status, another RDECC_4_0 transaction should be sent out to the next address,

incremented by 16 [Data Unit size/8] bytes.

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