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28HS01GTAM03 数据表(PDF) 10 Page - Infineon Technologies AG |
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28HS01GTAM03 数据表(HTML) 10 Page - Infineon Technologies AG |
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10 / 138 page  Datasheet 10 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Interface overview 2.2 Signal protocols 2.2.1 SEMPER™ Flash octal and SPI clock modes The SEMPER™ Flash with Octal interface device can be driven by an embedded microcontroller (bus master) in either of the following two clocking modes: • Mode 0 with Clock Polarity LOW at the fall of CS# and staying LOW until it goes HIGH at capture input. • Mode 3 with Clock Polarity HIGH at the fall of CS# then going LOW to HIGH at capture input. For these two modes, data is latched into the device on the rising edge of the CK signal in SDR protocol and both edges of the CK signal in DDR protocol. The output data in SDR protocol is available on the falling edge of the CK clock signal and the output data in DDR protocol is available on the rising edge of the CK clock signal. The difference between the two modes is the clock polarity when the bus master is in Standby mode and not transferring any data. Figure 3 SPI SDR mode support Figure 4 Octal SDR mode support |
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