28HS01GTAM03 datasheet(64/138 Pages) INFINEON

64 / 138 page

Datasheet

64 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.11.6

Erase related registers and transaction

4.12

Suspend and resume embedded operation

HL-T/HS-T device can interrupt and suspend the running embedded operations such as Erase, Program or Data

Integrity Check. It can also resume the suspended operation once the host finishes the intermediate operation

and sends the respective resume transaction to the device.

4.12.1

Erase, program or data integrity check suspend

The Suspend transaction allows the system to interrupt a program, erase, or data integrity check operation and

then read from any other non erase-suspended sector, non-program-suspended-page, or the array. The Device

Ready/Busy Status Flag (RDYBSY) in Status Register 1 (STR1V[0]) must be checked to know when the program,

erase, or data integrity check operation has stopped.

4.12.1.1

Program suspend

• Program Suspend is valid only during a programming operation.

• The Program Operation Suspend Status flag (PROGMS) in Status Register-2 (STR2V[0]) can be used to determine

if a programming operation has been suspended or was completed at the time RDYBSY changes to 0.

• A program operation can be suspended to allow a read operation.

• Reading at any address within a program-suspended page produces undetermined data.

4.12.1.2

Erase suspend

• Erase Suspend is valid only during a sector erase operation.

• The Erase operation Suspend status flag (ERASES) in Status Register-2 (STR2V[1]) can be used to determine if

an erase operation has been suspended or was completed at the time RDYBSY changes to 0.

• A Chip Erase operation cannot be suspended.

• An Erase operation can be suspended to allow a program operation or a read operation.

• During an erase suspend, the DYB array can be read to examine sector protection.

• A new erase operation is not allowed with an already suspended erase, program, or data integrity check

operation. An erase command is ignored in this situation.

• Reading at any address within an erase-suspended sector produces undetermined data.

Table 34

Erase related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 (STR1N, STR1V)

(see Table 41 on page 76)

Write Enable (WRENB_0_0)

Status Register 2 (STR2V)

(see Table 44 on page 78)

Erase 4KB Sector (ER004_4_0)

Configuration Register 5 (CFR5N, CFR5V)

(see Table 54 on page 85)

Erase 256KB Sector (ER256_4_0)

ASP PPB Lock (PPLV)

(see Table 63 on page 89)

Erase Chip (ERCHP_0_0)

ECC Status Register (ECSV)

(see Table 58 on page 86)

Evaluate Erase Status (EVERS_4_0)

Sector Erase Count Register (SECV)

(see Table 67 on page 90)

Sector Erase Count (SEERC_4_0)

Erase Persistent Protection Bit (PPB) Transaction

(ERPPB_0_0)

Erase Persistent Protection Bit (PPB) Transaction

(ERPPB_0_0)

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