28HS01GTAM03 datasheet(52/138 Pages) INFINEON

52 / 138 page

Datasheet

52 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.6.1.2

Microcontroller initialization failure detection Related Registers and

Transactions

4.6.2

Configuration corruption detection

If during device’s configuration update, such as writing to a nonvolatile register, a power loss occurs or a

hardware reset is initiated, the write any register transaction will get interrupted. The device will return to

Standby mode, but the nonvolatile register data is most likely corrupted since the embedded write operation was

prematurely terminated. During the next power-up, the configuration corruption is detected and the device

reverts to its Default Boot mode (1S-1S-1S) and allows rewriting the configuration again. The device will maintain

the configured protection scheme.

Table 25 shows the device’s Status Register bits upon detecting a configuration corruption.

Table 24

Microcontroller initialization failure related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 Volatile (STR1V)

(see Table 41 on page 76)

Read Any Register (RDARG_C_0)

N/A

Read Status Register -1 (RDSR1_0_0)

Table 25

Status register 1 configuration corruption detection signature

Bit

Field name

Function

Detection

signature

STR1V[7]

RESRVD

Reserved for Future Use

STR1V[6]

PRGERR

Programming Error Status Flag

STR1V[5]

ERSERR

Erasing Error Status Flag

STR1V[4]

LBPROT[2:0]

Legacy Block Protection based memory Array size selection

Note LBPRIT[2:0] can be anything from 000 to 111 based on Block Protection configuration

STR1V[3]

STR1V[2]

STR1V[1]

WRPGEN

Write/Program Enable Status Flag

STR1V[0]

RDYBSY

Device Ready/Busy Status Flag

Table 26

Interface configuration upon detecting configuration corruption

Interface

Transactions

supported

Address

(# of bytes)

Frequency of

operation

(# of clock cycles)

Output impedance

SPI (1S-1S-1S)

All SPI (1S-1S-1S)

Transactions

4Maximum

45

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