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28HS01GTAM03 数据表(PDF) 86 Page - Infineon Technologies AG

部件名 28HS01GTAM03
功能描述  S256Mb/512Mb/1Gb SEMPER??Flash Octal interface, 1.8V/3.0V
PDF  138 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

28HS01GTAM03 数据表(HTML) 86 Page - Infineon Technologies AG

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002-18216 Rev. *W
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
Octal interface, 1.8V/3.0V
Registers
5.11
Memory array data integrity check CRC register (DCRV)
The memory array Data Integrity Check CRC Register (DCRV) stores the results of the CRC calculation on the data
contained between the specified starting and ending addresses.
5.12
ECC status register (ESCV)
The ECC Status Register (ESCV) contains the ECC status of any error correction action performed on the unit data
whose byte was addressed during last read.
Note Unit data is defined as the number of bytes over which the ECC is calculated. HL-T/HS-T family devices have
a 16 bytes (128 bits) unit data.
Table 57
Memory array data integrity check CRC register
Bit
number
Name
Function
Read/Write
N = Nonvolatile
V = Volatile
Factory default
(binary)
Description
DCRV[31:0] DTCRCV[31:0]
Memory Array Data
CRC Checksum
Value
V -> R
0x00000000
Description: The DTCRCV[31:0 bits store the checksum value of
the CRC process on the memory array data contained within the
starting address and the ending address.
Selection Options: Checksum Value
Dependency: N/A
Table 58
ECC status register
Bit
number
Name
Function
Read/Write
N = Nonvolatile
V = Volatile
Factory default
(binary)
Description
ECSV[7:5]
RESRVD
Reserved for Future
Use
V -> R
000
This bit is Reserved for future use. This bit must always be
written/loaded to its default state.
ECSV[4]
ECC2BT
ECC Error 2-bit Error
Detection Flag
V -> R
0
Description: The ECC2BT bit indicates that a 2-bit ECC Error was
detected in the data unit (16 bytes). A Clear ECC Status Register
transaction (CLECC_0_0) will reset ECC2BT.
Note ECC2BT is updated every time any memory address is read
and is sticky, i.e. once it is set, it remains set. The ECC2BT status
is maintained until a Clear ECC Status Register transaction
(CLECC_0_0) is executed.
Note ECC1BT is not valid if ECC2BT status flag is set.
Selection Options:
0 = No 2-Bit ECC Error was detected in the data unit (16 bytes)
1 = 2-bit ECC Error was detected in the data unit (16 bytes)
Dependency: CFR4x[3]
ECSV[3]
ECC1BT
ECC Error 1-bit Error
Detection and
Correction Flag
V -> R
0
Description: The ECC1BT bit indicates that a 1-bit ECC Error was
detected and corrected in the data unit (16 bytes). A Clear ECC
Status Register transaction (CLECC_0_0) will reset ECC1BT.
Note ECC1BT is updated every time any memory address is read
and is sticky, i.e. once it is set, it remains set. The ECC1BT status
is maintained until a Clear ECC Status Register transaction
(CLECC_0_0) is executed.
Selection Options:
0 = No 1-Bit ECC Error was detected in the data unit (16 bytes)
1 = 1-bit ECC Error was detected in the data unit (16 bytes)
Dependency: N/A
ECSV[2:0]
RESRVD
Reserved for Future
Use
V -> R
000
This bit is Reserved for future use. This bit must always be
written/loaded to its default state.



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