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28HS01GTAM03 数据表(PDF) 83 Page - Infineon Technologies AG |
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28HS01GTAM03 数据表(HTML) 83 Page - Infineon Technologies AG |
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83 / 138 page  Datasheet 83 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Registers 5.7 Configuration register 4 (CFR4x) Configuration Register 4 controls the main Flash array read transactions burst wrap behavior and output driver impedance. Table 51 Register latency code (cycles) versus frequency[29, 31] Latency code SDR SPI register transaction latency dummy cycles (1S-1S-1S)[28] SDR octal register transactions latency dummy cycle (8S-8S-8S) DDR octal register transactions latency dummy cycle (8D-8D-D8) Frequency RDARG_C_0[30] RDDYB_4_0 RDPLB_0_0 RDIDN_0_0 RDSR1_0_0 RDSR2_0_0 Frequency RDARG_4_0[30] RDPLB_4_0 RDDYB_4_0 RDIDN_4_0 RDSR1_4_0 RDSR2_4_0 Frequency RDARG_4_0[30] RDPLB_4_0 RDDYB_4_0 RDIDN_4_0 RDSR1_4_0 RDSR2_4_0 00 50MHz 0 0 50MHz 3 25MHz 3 01 133MHz 1 0 133MHz 4 66MHz 4 10 133MHz 1 1 166MHz 5 166MHz (HL-T) / 200MHz (HS-T) 5 11 166MHz 2 2 200MHz 6 200MHz 6 Notes 28. CK frequency > 166MHz SDR, is not supported. 29. RDUID_4_0 alway has 32 cycles of latency. Maximum frequency under SDR SPI is 166MHz, under HS-T SDR/DDR Octal is 200MHz and under HL-T SDR/DDR Octal is 166MHz. 30. RDARG_C_0 and RDARG_4_0 uses these dummy cycles for reading volatile registers. 31. RDCRC_4_0 alway has 8 cycles of latency. Maximum frequency under SDR SPI is 166MHz, under HS-T SDR/DDR Octal is 200MHz and under HL-T SDR/DDR Octal is 166MHz Table 52 Configuration register 4 Bit number Name Function Read/Write N = Nonvolatile V = Volatile Factory default (binary) Description CFR4N[7:5] CFR4V[7:5] IOIMPD[2:0] I/O Driver Output Impedance selection N -> R/W V -> R/W 101 Description: The IOIMPD[2:0] bits select the IO driver output impedance (drive strength). The output impedance configu- ration bits adjust the drive strength during normal device operation to meet system signal integrity requirements. Selection Options: 000 = 45Ω 001 = 120Ω 010 = 90Ω 011 = 60Ω 100 = 45Ω 101 = 30Ω (Factory Default) 110 = 20Ω 111 = 15Ω Dependency: N/A CFR4N[4] CFR4V[4] RBSTWP Read Burst Wrap Enable selection N -> R/W V -> R/W 0 Description: The RBSTWP bit selects the read burst wrap feature. It allows the device to enter and exit burst wrapped read mode during normal operation. The wrap length is selected by RBSTWL[1:0] bits. Selection Options: 0 = Read Wrapped Burst disabled 1 = Read Wrapped Burst enabled Dependency: RBSTWL[1:0] (CFR4x[1:0]) CFR4N[3] CFR4V[3] ECC12S Error Correction Code (ECC) 1-bit or 1-bit/2-bit error correction selection N -> R/W V -> R/W 1 Description: The ECC12S bit selects between 1-bit ECC error detection/correction or both 1-bit ECC error detection and correction and 2-bit ECC error detection. This configuration option affects Address Trap Register and ECC Counter Register functionalities as well. The host needs to erase and reprogram the data in the SEMPER™ Flash memory upon ECC configuration change (1-bit correction to 1-bit correction and 2-bit detection or vice versa). Selection Options: 0 = 1-bit ECC Error Detection/Correction 1 = 1-bit ECC Error Detection/Correction and 2-bit ECC error detection Dependency: N/A |
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