28HS01GTAM03 datasheet(100/138 Pages) INFINEON

100 / 138 page

access

CLPEF_0_0

Clear Program and Erase

Failure Flags transaction

resets STR1V[5] (Erase failure

flag) and STR1V[6] (Program

failure flag)

(CMD)

Figure 18/

Figure 19

166 / 200

N/A

ECC

RDECC_4_0

Read ECC Status is used to

determine the ECC status of

the addressed data unit.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 27/

Figure 29

CLECC_0_0

Clear ECC Status Register

transaction resets ECC Status

Detection), ECC Status

Correction), Address Trap

Counter.

(CMD)

Figure 18/

Figure 19

N/A

CRC

RDCRC_4_0

Read Interface CRC Register

transaction allows the

volatile Interface CRC

(CMD)

(ADDR)

Figure 27/

Figure 28

DICHK_4_1

Data Integrity Check trans-

action causes the device to

perform a Data Integrity

Check over a user defined

address range.

(CMD)

(ADDR)

Start

ADDR

[31:24]

Start

ADDR

[23:16]

Start

ADDR

[15:8]

Start

ADDR

[7:0]

End

ADDR

[31:24]

End

ADDR

[23:16]

End

ADDR

[15:8]

End

ADDR

[7:0]

Figure 22/

Figure 23

Read flash

array

RDAY1_4_0

Read Octal SDR transaction

reads out the memory

contents at the given address

on DQ[7:0]. The maximum CK

frequency for this SDR trans-

action is 200-MHz frequency

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 27

RDAY2_4_0

Read Octal DDR transaction

reads out the memory

contents at the given address

on DQ[7:0]. The maximum CK

frequency for this DDR trans-

action is 200-MHz frequency

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 28

Program

flash array

PRPGE_4_1

Program Page programs

256B or 512B data to the

memory array in one trans-

action.

WRENB_

0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data 1

[7:0]

Input

Data 2

[7:0]

(Conti

nue)

Figure 24/

Figure 25

Table 78

Octal (8S-8S-8S, 8D-8D-8D) transaction table (Continued)

Note

32. In case of Octal DDR protocol.

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