28HS01GTAM03 datasheet(40/138 Pages) INFINEON

40 / 138 page

Datasheet

40 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.4

Data integrity CRC

HL-T/HS-T family devices have a group of transactions to perform a hardware accelerated CRC calculation over

a user defined address range in the memory array. The calculation is another type of embedded operation similar

to programming or erase in which the device is busy while the calculation is in progress. The CRC operation uses

the same CRC32 polynomial as Interface CRC to determine the CRC check-value.

CRC32 Polynomial: X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1

The check-value generation sequence is started by entering the DICHK_4_1 transaction. The transaction includes

loading the beginning address into the CRC Start Address Register and identifying the beginning of the address

range that will be covered by the CRC calculation. The transaction also includes loading the ending address into

the CRC End Address Register. Bringing CS# HIGH starts the CRC calculation. The CRC process calculates the

check-value on the data contained at the starting address through the ending address.

During the calculation period the device goes into the Busy state (STR1V[0] - RDYBSY = 1). Once the check-value

calculation is completed, the device returns to the Ready state (STR1V[0] - RDYBSY = 0) and the calculated

check-value is available to be read. The check-value is stored in the Data Integrity CRC Register (DCRV[31:0]) and

can be read using Read Any Register transaction.

The check-value calculation can only be initiated when the device is in Standby State; and once started it can be

suspended with the CRC Suspend transaction (SPEPD_0_0) to read data from the memory array. During the

Suspended state the CRC Suspend Status Bit in the Status Register 2 will be set (STR2V[4] - DICRCS = 1). Once

suspended, the host can read the Status Register, read data from the array and can resume the CRC calculation

by using the CRC Resume transaction RSEPD_0_0.

The Ending Address (ENDADD) must be at least two addresses higher than the Starting Address (STRADD). If

ENDADD < STRADD + 3, the check-value calculation will abort and the device will return to the Ready state

(STR1V[0] - RDYBSY = 0). Data Integrity CRC abort status bit will be set (STR2V[3] - DICRCA = 1) to indicate the

aborted condition. The DICRCA bit can be cleared, once set, by Software reset or a valid subsequent CRC

command execution. If ENDADD < STRADD + 3, the check-value will hold indeterminate data.

Note Any invalid transaction during CRC check-value calculation can corrupt the check-value data.

4.4.1

Data integrity check related registers and transactions

Table 16

Data integrity CRC related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 (STR1N, STR1V)

(see Table 41 on page 76)

Data Integrity Check (DICHK_4_1)

Status Register 2 (STR2V)

(see Table 44 on page 78)

Suspend Erase/Program/Data Integrity Check

(SPEPD_0_0)

Suspend Erase/Program/Data Integrity Check

(SPEPD_0_0)

Data Integrity CRC Check-Value Register (DCRV)

(see Table 57 on page 86)

Resume Erase/Program/ Data Integrity Check

(RSEPD_0_0)

Resume Erase/Program/ Data Integrity Check

(RSEPD_0_0)

28HS01GTAM03 数据表(PDF) 40 Page - Infineon Technologies AG

28HS01GTAM03 数据表(HTML) 40 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载