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28HS01GTAM03 数据表(PDF) 79 Page - Infineon Technologies AG |
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28HS01GTAM03 数据表(HTML) 79 Page - Infineon Technologies AG |
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79 / 138 page  Datasheet 79 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Registers 5.4 Configuration register 1 (CFR1x) Configuration Register 1 controls interface and data protection functions. Table 45 Configuration register 1 Bit number Name Function Read/Write N = Nonvolatile V = Volatile Factory default (binary) Description CFR1N[7] CFR1V[7] RESRVD Reserved for Future Use N -> R/W V -> R/W 0 This bit is Reserved for future use. This bit must always be written/loaded to its default state. CFR1N[6] CFR1V[6] SP4KBS Split 4KB Sectors selection between top and bottom address space If PLPROT = 0 N -> R/W V -> R If PLPROT = 1 N -> R V -> R 0 Description: The SP4KBS bit selects whether the 4KB sectors are grouped together or evenly split between High and LOW address ranges. Selection Options: 0 = 4KB Sectors are grouped together 1 = 4KB Sectors are split between High and Low Addresses Dependency: TB4KBS(CFR1N[2]) CFR1N[5] CFR1V[5] TBPROT Top or Bottom Protection selection for Legacy Protection Mode If PLPROT = 0 N -> R/W V -> R If PLPROT = 1 N -> R V -> R 0 Description: The TBPROT bit selects the reference point of the Legacy Block Protection bits (LBPROT[2:0]) in the Status Register on whether the protection starts from the top or starts from the bottom of the address range. The bit also selects a memory address range (lowest or highest) to remain readable is available for reading during Read Password Protection mode even before a successful Password entry is completed. Selection Options: 0 = Legacy Protection is applicable in the top half of the address range 1 = Legacy Protection is applicable in the bottom half of the address range Dependency: LBPROT[2:0] (STR1x[3:1]) CFR1N[4] CFR1V[4] PLPROT Permanent Locking selection of Legacy Block Protection and 4KB Sector Architecture N -> R/1 V -> R 0 Description: The PLPROT bit permanently protects the Legacy Block Protection and 4KB Sector location. It thereby permanently protects the memory array protection scheme and sector architecture. Note PLPROT protects LBPROT[2:0], SP4KBS, TBPROT, and TB4KBS bits from program and erase, and it is recommended to configure these bits before configuring the PLPROT bit. Selection Options: 0 = Legacy Block Protection and 4KB Sector Location are not protected 1 = Legacy Block Protection and 4KB Sector Location are protected Dependency: N/A CFR1N[3] CFR1V[3] RESRVD Reserved for Future Use N -> R/W V -> R/W 0 This bit is Reserved for future use. This bit must always be written/loaded to its default state. CFR1N[2] CFR1V[2] TB4KBS Top or Bottom Address Range selection for 4KB Sector Block If PLPROT = 0 N -> R/W V -> R If PLPROT = 1 N -> R V -> R 0 Description: The TB4KBS bit defines the logical address location of the 4KB sector block. The 4KB sector block replaces the fitting portion of the highest or lowest address sector. Selection Options: 0 = 4KB Sector Block is in the bottom of the memory address space 1 = 4KB Sector Block is in the top of the memory address space Dependency: SP4KBS (CFR1x[6]) CFR1N[1] CFR1V[1] RESRVD Reserved for Future Use N -> R/W V -> R/W 0 This bit is Reserved for future use. This bit must always be written/loaded to its default state. CFR1N[0] CFR1V[0] TLPROT Temporary Locking selection of Legacy Block Protection and Sector Archi- tecture N -> R V -> R/W 0 Description: The TLPROT bit temporarily protects the Legacy Block Protection and 4KB Sector location. Upon power-up or a hardware reset, TLPROT is set to its default state. When selected, it protects the memory array protection scheme and sector architecture from any changes. Note TLPROT protects LBPROT[2:0], SP4KBS, TBPROT, and TB4KBS bits from program and erase. Selection Options: 0 = Legacy Block Protection and 4KB Sector Location are not protected 1 = Legacy Block Protection and 4KB Sector Location are temporarily protected Dependency: N/A |
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