28HS01GTAM03 datasheet(58/138 Pages) INFINEON

58 / 138 page

Datasheet

58 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.8.3.7

Read register related registers and transactions

4.8.4

Data strobe (DS)

A data strobe (DS) is transmitted externally, along with data, for use in data capture at the host. During the period

of data transfer in read transactions, the DS signal is driven by the device and transitions with the DQ signal data

transitions. DS is used as an additional output signal with the same timing characteristics as other data outputs

but with the guarantee of transitioning with every data bit transferred. DS is edge-aligned with data for DDR

READs and is center-aligned with data for SDR READs. A pre-drive on DS exists to ensure DS is driven LOW immedi-

ately after 2.5 clock cycle after last address byte input to the device.

4.9

Write transactions

There are write transactions for writing to the Registers. These write transactions can use any of following three

protocols:

• SPI interface with SDR (1S-1S-1S) protocol, transfers the one byte command one bit per CK rising edge

• Octal interface with SDR (8S-8S-8S) protocol, transfers the two byte command eight bits per CK rising edge

• Octalinterface with DDR(8D-8D-8D) protocol,transfersthe two byte command eight bits per CK rising and falling

edge

4.9.1

Write enable transaction

The Write Enable (WRENB_0_0) transaction sets the Write Program Enable Status (WRPGEN) bit of the Status

to enable write, program, and erase transactions (see Transaction table on page 95).

4.9.2

Write disable transaction

The Write Disable (WRDIS_0_0) transaction clears the Write Program Enable Status (WRPGEN) bit of the Status

The WRPGEN bit can be cleared to 0 by issuing the Write Disable (WRDIS_0_0) transaction to disable commands

that requires WRPGEN be set to 1 for execution. The WRDIS_0_0 transaction can be used by the user to protect

memory areas against inadvertent write, program, or erase operations that can corrupt the contents of the

memory. The WRDIS_0_0 transaction is ignored during an embedded operation while RDYBSY bit = 1 (STR1V[0])

(see Transaction table on page 95).

Table 31

Read register related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Configuration Register 2 (CFR2N, CFR2V)

(see Table 48 on page 80)

Read Any Register (RDARG_C_0)

Read Any Register (RDARG_4_0)

Configuration Register 3 (CFR3N, CFR3V)

(see Table 50 on page 82)

Configuration Register 5 (CFR5N, CFR5V)

(see

Table 54 on page 85)

Read Status Register 1 (RDSR1_0_0)

Read Status Register 1 (RDSR1_4_0)

Read Status Register 2 (RDSR2_0_0)

Read Status Register 2 (RDSR2_4_0)

Read DYB (RDDYB_4_0)

Read PPB (RDPPB_4_0)

Read PPB Lock (RDPLB_0_0)

Read PPB Lock (RDPLB_4_0)

Read ECC Status (RDECC_4_0)

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