28HS01GTAM03 datasheet(54/138 Pages) INFINEON

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Datasheet

54 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.7

AutoBoot

AutoBoot allows the host to read data from HL-T/HS-T family of devices after power up or after a hardware reset

without having to send any read transactions (including the address). Based on the device configuration, data is

output on the interface I/Os once CS# is brought LOW and CK is toggled.

The starting address for the read data is specified in the AutoBoot Register (ATBN[31:9] - STADR[22:0]). This

starting address can be at any page boundary location in the memory (512 byte page boundary). Also identified

in the AutoBoot Register is a starting delay which is represented as the number of clock cycles (ATBN[8:1] -

STDLY[7:0]). This delay is instituted before the data is read out. The delay can be programmed to meet the host's

requirements but a minimum amount is required to meet the memory access times based on the frequency for

operation. It is highly recommended to check the Status Register 1 value after successful or unsuccessful

AutoBoot execution to verify the configuration corruption (SafeBoot).

Notes

• Wrap function must be disabled for AutoBoot.

• AutoBoot is disabled when the Read Password feature is enabled, as part of the Advanced Sector Protection. It

is recommended to disable AutoBoot (ATBN[0] - ATBTEN) when Read Password feature is enabled.

• Autoboot with Interface CRC enabled requires reading out at least 4 words of data.

• It is highly recommended to assign first AutoBoot address in the Long Retention region.

4.7.1

AutoBoot related registers and transactions

4.8

Read transactions

HL-T/HS-T supports different read transactions to access different memory maps, namely: Read Memory array,

Read Device Identification, Read Register, Read Secure Silicon, Read Protection DYB and PPB bits.

These read transactions can use any of these three interfaces and protocols:

• SPI interface with SDR (1S-1S-1S) protocol, transfers the one byte command one bit per CK rising edge

• Octal output interface with SDR (1S-1S-8S) protocol, transfers the one byte command one bit per CK rising edge

(HL256T and HS256T Only)

• Octal interface with SDR (8S-8S-8S) protocol, transfers the two byte command eight bits per CK rising edge

• Octalinterface with DDR(8D-8D-8D) protocol,transfersthe two byte command eight bits per CK rising and falling

edge

These read transactions use the following features:

• The read transactions require latency cycles following the address to allow time to access the memory array

(except RDAY1_4_0 and RDAY1_C_0 of 1S-1S-1S protocol) (see Table 49).

• Data Strobe (DS) output enables the memory controller to capture data at the center of the data eye

(see Data strobe (DS) on page 58).

• The read transaction has the option of wrapped read length and alignment groups of 8-, 16-, 32-, or 64-bytes

(see Table 52 and Table 53).

Table 28

AutoBoot related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

AutoBoot Register (ATBN)

(see Table 66 on page 90)

Read Any Register (RDARG_C_0)

Read Any Register (RDARG_4_0)

Write Any Register (WRARG_C_1)

Write Any Register (WRARG_4_1)

AutoBoot Transaction (see Figure 14 on page 15)

AutoBoot Octal SDR Transaction

(see Figure 30 on page 21) / AutoBoot Octal DDR

Transaction (see Figure 31 on page 21))

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