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28HS01GTAM03 数据表(PDF) 46 Page - Infineon Technologies AG |
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28HS01GTAM03 数据表(HTML) 46 Page - Infineon Technologies AG |
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46 / 138 page ![]() Datasheet 46 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Features Figure 48 Permanent PPB sector protection flowchart 4.5.2.5 Temporary PPB protection scheme PPB based nonvolatile protection architecture can be temporarily locked where erasing and programming of the individual PPB bits is inhibited. The Persistent Protection Lock Bit (PPBLock) is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs and when set to 1, it allows the PPBs to be changed. There is only one PPB Lock Bit per device. The PPBLock transaction (WRPLB_0_0) is used to clear the bit to 0. The PPB Lock Bit must be cleared to 0 only after all the PPBs are configured to the desired settings. The PPB Lock Bit is set to 1 during POR or a Hardware Reset. When cleared with the PPBLock transaction, no software command sequence can set PPBLock, only another Hardware Reset or Power-Up can set PPBLock. Note Temporary PPB Protection does not require any ASP configuration. 4.5.2.6 Password protection scheme Password Protection scheme allows an even higher level of security by requiring a 64-bit password for setting PPBLock. In addition to this password requirement, after Power-Up or Hardware Reset, the PPB Lock Bit is cleared to 0 to ensure protection at Power-Up. Successful execution of the Password Unlock command by entering the entire password sets the PPB Lock Bit to 1, allowing for sector PPB modifications. Selecting bit 2 in Advanced Sector Protection Register (ASPO[2] - ASPPWD) selects the Password Protection scheme. Password Protection scheme also protects ASPO from write or program. Note A password must be programmed before selecting the password protection scheme. The password unlock SPI transaction (PWDUL_0_1) or Octal transaction (PWDUL_4_1) is used to provide a password for comparison. The Password Protection scheme flowchart is shown in Figure 49. |
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