28HS01GTAM03 datasheet(66/138 Pages) INFINEON

66 / 138 page

Datasheet

66 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.12.2

Erase, program or data integrity check resume

An Erase, Program or Data Integrity Check Resume transaction must be written to resume a suspended operation.

After program or read operations are completed during a Program, Erase, or Data Integrity Check suspend, the

Resume transaction is sent to resume the suspended operation.

After an Erase, Program or Data Integrity Check Resume transaction is issued, the RDYBSY bit in Status Register

1 will be set to a 1 and the programming operation will resume if one is suspended. If no program operation is

suspended, the suspended erase operation will resume. If there is no suspended program, erase or data integrity

check operation, the resume transaction is ignored.

Program, Erase or Data Integrity Check operations may be interrupted as often as necessary. For example, a

program suspend transaction could immediately follow a program resume transaction, but for a program or

erase operation to progress to completion there must be some period of time between resume and the next

suspend transaction greater than or equal to tPEDRS. Figure 54 shows the flow of suspend and resume operation.

Figure 54

Suspend and resume sequence

4.12.3

Suspend and resume related registers and transactions

Table 36

Suspend and resume related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 (STR1N, STR1V)

(see Table 41 on page 76)

Suspend Erase / Program / Data Integrity Check

(SPEPD_0_0)

Suspend Erase / Program / Data Integrity Check

(SPEPD_0_0)

Status Register 2 (STR2V)

(see Table 44 on page 78)

Resume Erase / Program / Data Integrity Check

(RSEPD_0_0)

Resume Erase / Program / Data Integrity Check

(RSEPD_0_0)

Read Any Register (RDARG_C_0)

Read Any Register (RDARG_4_0)

Read Status Register -1 (RDSR1_0_0)

Read Status Register -1 (RDSR1_4_0)

Read Status Register -2 (RDSR2_0_0)

Read Status Register -2 (RDSR2_4_0)

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