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28HS01GTAM03 数据表(PDF) 13 Page - Infineon Technologies AG |
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28HS01GTAM03 数据表(HTML) 13 Page - Infineon Technologies AG |
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13 / 138 page ![]() Datasheet 13 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Interface overview • In this protocol, during the period of data transfer in a read transaction, the Data Strobe (DS) signal is driven by the flash device and transitions are synchronized (Edge aligned in DDR and center aligned in SDR protocol) with the DQ signal data transitions. DS is used as an additional output signal with the same timing characteristics as other data outputs but with the guarantee of transitioning with every data bit transferred. Serial peripheral interface (SPI, 1S-1S-1S) on page 13 and SPI program transaction with command and octal address, data input (1S-8S-8S) on page 17 show all transaction formats by protocol mode. 2.3.1 Serial peripheral interface (SPI, 1S-1S-1S) Figure 6 SPI transaction with command input Figure 7 SPI transaction with command and address input Figure 8 SPI transaction with command and two input addresses |
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