LTM4686BIVPBF datasheet(26/130 Pages) AD

26 / 130 page

LTM4686B

Rev. 0

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OPERATION

When an external stimulus pulls the LTM4686B’s GPIOn

pin(s) logic low, the respective channel (VOUTn) either: takes

no action on it, i.e., ignores it completely—if MFR_GPIO_

RESPONSEn = 0x00; or, turns off immediately, i.e., the

power stage(s) become high impedance (“inhibited”)—if

MFR_GPIO_RESPONSEn = 0xC0.

The MFR_GPIO_PROPAGATEn register contents config-

ure which fault(s) cause the LTM4686B to pull its GPIOn

pin(s) logic low.

I2C communications are originated by the user’s (sys-

tem’s)I2C master device. Writes/reads to/from Channel 0

of the LTM4686B (VOUT0: PAGE 0x00), to/from Channel

1 of the LTM4686B (VOUT1: PAGE 0x01), or writes to

both Channels 0 and 1 of the LTM4686B (VOUT0 and

VOUT1: PAGE 0xFF) are possible. The target channel(s)

of interest are selected by the I2C master by executing

the PAGE command and sending the appropriate argu-

ment (0x00, 0x01, 0xFF) in the payload. The PAGE com-

mand is unrestricted, i.e., not affected by the WP pin or

WRITE_PROTECT register settings.

The LTM4686B always responds to its global slave

addresses, 0x5A and 0x5B. Commands sent to the global

address 0x5A act the same as if the PAGE command were

set to 0xFF, i.e., received commands are written to both

channels simultaneously. Commands sent to the global

address 0x5B are applied to the PAGE active at the time

of the global address transaction, i.e., allows channel-

specific command of all LTM4686B devices on the bus.

I2C commands not listed above that relate to Fault Status

and EEPROM NVM Operations follow. Writing of the fol-

lowing is possible provided the state of the WP (write

protect) pin and the WRITE_PROTECT register value per-

mits the I2C writes:

Soliciting (reading) module fault status and clear-

ing (writing) module fault status (CLEAR_FAULTS,

STATUS_BYTEn, STATUS_WORDn, STATUS_

VOUTn, STATUS_IOUTn, STATUS_INPUT, STATUS_

TEMPERATUREn, STATUS_CML [communications,

memory, and/or logic], and STATUS_MFR_SPECIFICn

[miscellaneous]).

Storing the LTM4686B’s user-writable RAM register

data to the EEPROM NVM (STORE_USER_ALL).

An alternate means to the STORE_USER_ALL command

to directly erase and write the LTM4686B’s EEPROM

contents, protected by unlock keys, to facilitate program-

ming of the LTM4686B EEPROM in environments such

as ICT (in-circuit test) and bulk programming by, e.g.,

embedded hardware or by the LTpowerPlay GUI. Also, a

means to directly read the LTM4686B EEPROM contents

(MFR_EE_UNLOCK, MFR_EE_ERASE, MFR_EE_DATA).

Instigating a soft reset of the LTM4686B without power-

cycling SVIN power (MFR_RESET). The MFR_RESET

command triggers the download of EEPROM NVM data

to RAM registers, as if SVIN power had been cycled.

Forcing a download of EEPROM NVM data to RAM reg-

isters (RESTORE_USER_ALL). This is indistinguish-

able from executing MFR_RESET.

Other data that can be obtained from the LTM4686B via

I2C communications are as follows:

Soliciting the LTM4686B for its PMBus capabilities, as

defined by PMBus (CAPABILITY):

• PEC (packet error checking). Note, the LTM4686B

requires valid PEC in I2C communications when

MFR_CONFIG_ALL[2] = 1b. The NVM factory-default

configuration is MFR_CONFIG_ALL[2] = 0b, i.e., PEC

not required.

• I2C communications can be supported at up to

400kHz SCL bus speed. Note, clock low extend-

ing (clock stretching) must be enabled on the

LTM4686B to ensure robust communications above

100kHz SCL bus speeds, i.e., MFR_CONFIG_ALL[1]

= 1b. The NVM factory-default configuration is

MFR_CONFIG_ALL[1] = 0b, i.e. Clock stretching

is disabled.

• The LTM4686B has an SMBALERT (ALERT) pin

and does support the SMBus ARA (alert response

address) protocol.

Soliciting the module for the maximum output voltage

it can be commanded to produce (MFR_VOUT_MAXn).

Soliciting the device for the data format of its output

voltage-related registers (VOUT_MODEn).

LTM4686BIVPBF 数据表(PDF) 26 Page - Analog Devices

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