LTM4686BIVPBF datasheet(34/130 Pages) AD

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LTM4686B

Rev. 0

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OPERATION

Rail addressing provides a means for the bus master to simul-

taneously communicate with all channels connected together

to produce a single output voltage (PolyPhase®). While simi-

lar to global addressing, the rail address can be dynamically

assigned with the paged MFR_RAIL_ADDRESS command,

allowing for any logical grouping of channels that might be

required for reliable system control. Do not read from rail

addresses because multiple ADI devices may respond.

Device addressing provides the standard means of the

PMBus master communicating with a single instance

of an LTM4686B. The value of the device address is set

by a combination of the ASEL configuration pin and the

MFR_ADDRESS command. When this addressing means

is used, the PAGE command determines the channel being

acted upon. Device addressing can be disabled by writing

a value of 0x80 to the MFR_ADDRESS.

All four means of PMBus addressing require the user to

employ disciplined planning to avoid addressing conflicts.

Communication to LTM4686B devices at global and rail

addresses should be limited to command write operations.

FAULT DETECTION AND HANDLING

A variety of fault and warning reporting and handling

mechanisms are available. Fault and warning detection

capabilities include:

Input OV/FAULT Protection and UV Warning

Average Input OC Warn

Output OV/UV Fault and Warn Protection

Output OC Fault and Warn Protection

Internal and External Overtemperature Fault and Warn

Protection

External Undertemperature Fault Protection

CML Fault (Communication, Memory or Logic)

External Fault Detection via the Bidirectional GPIOn Pins.

In addition, the LTM4686B can map any combination of fault

indicators to their respective GPIOn pin using the propagate

GPIOn response commands, MFR_GPIO_PROPAGATEn.

Typical usage of a GPIO pin is as a driver for an external

crowbar device, overtemperature alert, overvoltage alert or

as an interrupt to cause a microcontroller to poll the fault

commands. Alternatively, the GPIOn pins can be used as

inputs to detect external faults downstream of the control-

ler that require an immediate response. The GPIO0 and/or

GPIO1 pins can also be configured as power good outputs.

Power good indicates the controller output is within the OV/

UV fault thresholds. At power-up the pin will initially be three-

state. If it is necessary to have the desired polarity on the pin

at power-up in this configuration, attach a Schottky diode

between the RUN pin of the propagated power good signal

and the GPIO pin. The Cathode must be attached to RUN

and the Anode to the GPIO pin (see Figure 1). If the GPIO pin

is set to a power good status, the MFR_GPIO_RESPONSE

must be ignore otherwise a latched off condition exists.

As described in the Soft-Start section, it is possible to

control start-up through concatenated events. If GPIOn

is used to drive the RUN pin of another controller, the

unfiltered VOUT_UV fault limit should be mapped to the

GPIOn pin.

Any fault or warning event will cause the ALERT pin to

assert low unless the ALERT is masked by the SMBALERT_

MASK command. The pin will remain asserted low until

the CLEAR_FAULTS command is issued, the fault bit is

written to a 1, the PMBus master successfully reads the

device ARA register, bias power is cycled or a MFR_RESET

or RESTORE_USER_ALL command is issued. Channel

specific faults are cleared if the RUN pins are toggled OFF/

ON or the part is commanded OFF/ON via PMBus. If bit

0 of MFR_CONFIG_ALL is set to a 1, toggling the RUN

pins OFF/ON or commanding the part OFF/ON via PMBus

clears all faults. The MFR_GPIO_PROPAGATEn com-

mand determines if the GPIO pins are pulled low when a

fault is detected; however, the ALERT pin is always pulled

low if a fault or warning is detected and the status bits

are updated unless the ALERT pin is masked using the

SMBALERT_MASK command.

Output and input fault event handling is controlled by the

corresponding fault response byte as specified in Table 24

to Table 28. Shutdown recovery from these types of faults

can either be autonomous or latched. For autonomous

recovery, the faults are not latched, so if the fault condi-

tion is not present after the retry interval has elapsed, a new

soft-start is attempted. If the fault persists, the controller

LTM4686BIVPBF 数据表(PDF) 34 Page - Analog Devices

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