LTM4686BIVPBF datasheet(21/130 Pages) AD

21 / 130 page

LTM4686B

Rev. 0

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OPERATION

POWER MODULE INTRODUCTION

The LTM4686B is a highly configurable dual 14A (17A

peak) output standalone nonisolated switching mode step-

down DC/DC power supply with built-in EEPROM NVM

(nonvolatile memory) with ECC and I2C-based PMBus/

SMBus 2-wire serial communication interface capable

of 400kHz SCL bus speed. Two output voltages can be

regulated (VOUT0, VOUT1—collectively, VOUTn) with a few

external input and output capacitors and pull-up resistors.

Readback telemetry data of average input and output volt-

ages and currents, Channel PWM duty cycles, and mod-

ule temperatures are continually digitized cyclically by an

integrated 16-bit ADC (analog-to-digital converter). Many

fault thresholds and responses are customizable. Data can

be autonomously saved to EEPROM when a fault occurs,

and the resulting fault log can be retrieved over I2C at a

later time, for analysis.

The LTM4686B provides precisely regulated output volt-

ages between 0.5VDC to 3.6VDC (±0.5% above 1VDC,

±5mV below 1VDC). The target output voltage can be

set according to pin-strapping resistors (VOUTnCFG and

VTRIMnCFG pins), NVM/register settings, and altered on

the fly via the I2C interface. The output voltage can be

modified by the user at any time with a write to PMBus

VOUT_COMMAND. Executing this command has a typical

latency less than 10ms. Writes to PMBus OPERATION

have a typical latency less than 1ms. The NVM factory-

default switching frequency is 1MHz and the phase-

interleaving angle between its two channels is 180°.

Channel switching frequency, phase angle, and phase

relationship with respect to the falling edge of the SYNC

pin waveform can be configured according to a pin-strap

resistor (FSWPHCFG pin) and NVM/register settings—

though, not on the fly during regulation. The 7-bit I2C

slave address of the module defaults to the value retrieved

from MFR_ADDRESS[6:0] at power-up (factory default:

0x4F), but the least significant four bits of the address

are set by resistor pin-strapping the ASEL pin. Bits[6:4]

of MFR_ADDRESS can be written and stored to EEPROM.

Between the ASEL resistor pin-strap and user-configu-

rable MFR_ADDRESS[6:4], the LTM4686B can take on

any 7-bit slave address desired. With the exception of

the ASEL pin, the module can be configured to ignore all

pin-strap resistors, if desired (see MFR_CONFIG_ALL[6]).

Table 1 provides a summary of LTM4686B’s supported

PMBus commands. For details on the supported com-

mands, payloads and data formats see Appendix C: PMBus

Command Details.

For introductory information about the PMBus

Specification, see Appendix A: Similarity Between PMBus,

SMBus and I2C 2-Wire Interface. For information about

the data communication link layer and timing diagrams,

see Appendix B: PMBus Serial Digital Interface.

Major features of the LTM4686B strictly from a DC/DC

converter power delivery point of view are as follows:

Up to 14A (17A peak) Output Current Delivery from

Each of Two Integrated Power Stages (See Front Page

Figure)—or Up to 28A (34A peak) Output, Combined

(See Figure 29 and Figure 35).

DC/DC Step-Down Conversion from 4.5V to 5.75V

Input. (see Figure 29).

DC/DC Step-Down Conversion Possible from Less

Than 4.5V Input When an Auxiliary 5V Bias Supply

Powers SVIN and INTVCC (see Figure 31).

Wide Input Voltage Range: DC/DC Step-Down

Conversion from 2.375V to 5.75V Input, Driving SVIN

and INTVCC with ~5V Auxiliary Bias (see Test Circuit 2).

Output Voltage Range: 0.5V to 3.6V on both VOUT0 and

VOUT1.

Differential Remote Sensing of VOUT0 (VOSNS0+/

VOSNS0–). For paralleled outputs, the VOSNS0+/VOSNS0–

pin-pair can be configured as the feedback path for

both VOUT0 and VOUT1 (see Figure 35 and, optionally,

MFR_PWM_CONFIG[7]).

Start-Up Into a Prebiased Load Without Sinking Current.

Four LTM4686Bs Can Be Paralleled to Deliver Up to

~108A (See Figure 32).

One LTM4686B Can Be Paralleled with Three LTM4650

Modules to Deliver Up to 174A; Infer Rail Status

and Telemetry of Paralleled LTM4650 via the Sole

LTM4686B (See Figure 33).

Discontinuous Mode Operation Available for Higher

Light-Load Efficiency (MFR_PWM_MODEn[0]).

Output Current Limit and Overvoltage Protection.

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