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LTM4686BIVPBF 数据表(PDF) 9 Page - Analog Devices

部件名 LTM4686BIVPBF
功能描述  Ultrathin Dual 14A or Single 28A 關Module Regulator with Digital Power System Management
PDF  130 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTM4686BIVPBF 数据表(HTML) 9 Page - Analog Devices

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LTM4686B
9
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 5V, RUNn = 5V,
FREQUENCY_SWITCH = 1MHz, VOUT_COMMANDn = 1V and VOUT_UV_FAULT_RESPONSEn = TON_MAX_FAULT_RESPONSEn = 0x00
unless otherwise noted. All other command codes configured per factory-default EEPROM settings unless otherwise noted. Tested per
Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
EEPROM Characteristics
Endurance
(Note 13)
0°C ≤ TJ ≤ 85°C During EEPROM Write Operations (Note 3)
l
10,000
Cycles
Retention
(Note 13)
TJ < TJ(MAX), with Most Recent EEPROM Write Operation Having
Occurred at 0°C ≤ TJ ≤ 85°C (Note 3)
l
10
Years
Mass_Write
Mass Write Operation
Time
Execution of STORE_USER_ALL Command, 0°C ≤ TJ ≤ 85°C
(ATE-Tested at TJ = 25°C) (Notes 3, 13)
440
4100
ms
Digital I/Os
VIH
Input High Threshold
Voltage
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
1.35
1.8
V
V
VIL
Input Low Threshold
Voltage
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
0.8
0.6
V
V
VHYST
Input Hysteresis
SCL, SDA (Note 15)
80
mV
VOL
Output Low Voltage
SCL, SDA, ALERT, RUNn, GPIOn, SHARE_CLK:
ISINK = 3mA
l
0.3
0.4
V
IOL
Input Leakage Current SDA, SCL, ALERT, RUNn: 0V ≤ VPIN ≤ 5.5V
GPIOn and SHARE_CLK: 0V ≤ VPIN ≤ 3.6V
l
l
±5
±2
µA
µA
tFILTER
Input Digital Filtering
RUNn (Note 15)
GPIOn (Note 15)
10
3
µs
µs
CPIN
Input Capacitance
SCL, SDA, RUNn, GPIOn, SHARE_CLK, WP (Note 15)
10
pF
PMBus Interface Timing Characteristics
fSMB
Serial Bus Operating
Frequency
(Note 15)
10
400
kHz
tBUF
Bus Free Time
Between Stop and
Start
(Note 15)
1.3
μs
tHD,STA
Hold Time After
Repeated Start
Condition
Time Period After Which First Clock Is Generated (Note 15)
0.6
µs
tSU,STA
Repeated Start
Condition Setup Time
(Note 15)
0.6
μs
tSU,STO
Stop Condition Setup
Time
(Note 15)
0.6
μs
tHD,DAT
Data Hold Time
Receiving Data (Note 15)
Transmitting Data (Note 15)
0
0.3
0.9
µs
µs
tSU,DAT
Data Setup Time
Receiving Data (Note 15)
0.1
μs
tTIMEOUT_SMB
Stuck PMBus Timer
Timeout
Measured from the Last PMBus Start Event:
Block Reads, MFR_CONFIG_ALL[3] = 0b (Note 15)
Non-Block Reads, MFR_CONFIG_ALL[3] = 0b (Note 15)
MFR_CONFIG_ALL[3] = 1b (Note 15)
150
32
250
ms
ms
ms
tLOW
Serial Clock Low
Period
(Note 15)
1.3
10000
μs
tHIGH
Serial Clock High
Period
(Note 15)
0.6
μs



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