LTM4686BIVPBF datasheet(29/130 Pages) AD

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LTM4686B

Rev. 0

For more information www.analog.com

OPERATION

power stages are not connected together internal to the

module; therefore, DC/DC step-down conversion from

two different source power supplies can be performed.

Per Note 6 of the Electrical Characteristics section, the

output current may require derating for some operating

scenarios. Detailed derating guidance is provided in the

Applications Information section.

The LTM4686B contains dual integrated constant fre-

quency current mode control buck regulators (Channel

0 and Channel 1) whose built-in power MOSFETs are

capable of fast switching speed. The factory NVM-default

switching frequency clocks SYNC at 1MHz, to which the

regulators synchronize their switching frequency. The

default phase-interleaving angle between the channels

is 180°. A pin-strapping resistor on FSWPHCFG configures

the frequency of the SYNC clock (switching frequency)

and the channel phase relationship of the channels to

each other and with respect to the falling edge of the

SYNC signal. (Not all possible combinations of switch-

ing frequency and phase-angle assignments are settable

by resistor pin programming; see Table 4. Configure the

LTM4686B’s NVM to implement settings not available by

resistor-pin strapping.) When a FSWPHCFG pin-strap resis-

tor sets the channel phase relationship of the LTM4686B’s

channels, the SYNC clock is not driven by the module;

instead, SYNC becomes strictly a high impedance input

and channel switching frequency is then synchronized to

SYNC provided by an externally-generated clock or sib-

ling LTM4686B with pull-up resistor to VDD33. Switching

frequency and phase relationship can be altered via the

I2C interface, but only when switching action is off, i.e.,

when the module is not regulating either output. See the

Applications Information section for details.

Internal feedback loop compensation for Regulator 0

is available by connecting COMP0a to COMP0b. (For

Regulator 1, the connection is from COMP1a to COMP1b.)

With current mode control and internal feedback loop

compensation, the LTM4686B module has sufficient sta-

bility margins and good transient performance with a wide

range of output capacitors—even all-ceramic MLCCs.

Table 20 provides guidance on input and output capacitors

recommended for many common operating conditions.

The Analog Devices, Inc. μModule Power Design Tool is

available for transient and stability analysis. Furthermore,

expert users who prefer to not make use of the module’s

internal feedback loop compensation—but instead, tailor

the feedback loop compensation specifically for his/her

application—may do so by not connecting COMPna to

COMPnb: the personalized loop compensation network

can be applied externally, i.e., from COMPna to SGND,

and leaving COMPnb open circuit.

The LTM4686B has two general purpose input/output

pins, named GPIO0 and GPIO1. The behavior of these pins

is configurable via registers MFR_GPIO_PROPAGATEn

and MFR_GPIO_RESPONSEn. The GPIOn pins are high

impedance during NVM-download-to-RAM initialization.

These pins are intended to perform one of two primary

functions, or a hybrid of the two: behave as open-drain,

active low fault/warning indicators; and/or, behave as aux-

iliary RUN pins for their respective channels. In the former

case, the pins can be configured as interrupt pins, pulling

active low when output under/overvoltage, input under/

overvoltage, input/output overcurrent, overtemperature,

and/or communication, memory or logic (CML) fault or

warning events are detected by the LTM4686B. In the latter

case, the GPIOn pins can be bussed to paralleled siblings

(paralleled LTM4686B channels and/or modules), for pur-

poses of coordinating orderly power-up and power-down,

i.e., in unison. The LTM4686B DC/DC regulator does not

feature a traditional “power good” (PGOOD) indicator pin

to indicate when the output voltage is within a few percent

of the target regulation point. However, the GPIOn pin can

be configured as a PGOOD indicator—and this is, in fact,

its factory-default NVM setting. Suitable for event-based

sequencing of downstream rails, GPIOn is configured as

the unfiltered output of the VOUT_UV_FAULT_LIMITn

comparator, with Bit 12 of MFR_GPIO_PROPAGATEn =

“1b”; Bits 9 and 10 of MFR_GPIO_PROPAGATEn are not

set, since the propagation of power good in those latter

instances is subject to supervisor filtering and compara-

tor latency. If it is necessary to have the desired PGOOD

polarity appear on the GPIOn pin immediately upon SVIN

power-up—given that the pin will initially be high imped-

ance, until NVM contents have downloaded to RAM—a

pull-down Schottky diode is needed between the RUN

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