LTM4686BIVPBF datasheet(75/130 Pages) AD

75 / 130 page

LTM4686B

Rev. 0

For more information www.analog.com

TYPICAL APPLICATIONS

LTM4686B Paralleled with 3× LTM4650 (Up to 174A Output)

Figure 34. Current Sharing Performance of Figure 33 Circuit at 5VIN

CINH

22µF

×3

CINL

220µF

10k

×8

VIN

4.5V TO 5.75V

PWM CLOCK SYNCH.

TIME BASE SYNCH.

• SLAVE ADDRESS = 1000101_R/W (0x45)

• 1MHz SWITCHING FREQUENCY

• NO GUI CONFIGURATION AND NO

PART-SPECIFIC PROGRAMMING REQUIRED.

IN MULTI-MODULE SYSTEMS, CONFIGURING

RAIL_ADDRESS IS RECOMMENDED.

• SETTING MFR_PWM_CONFIG[7] = 1b,

CONFIGURES THE VOUT1 CONTROL LOOP

TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL-

SENSE PIN-PAIR AS THE FEEDBACK SIGNAL

FOR REGULATING VOUT1.

COUT

100µF

×10

VOUT, 3.3V

ADJUSTABLE

UP TO 28A (34A PEAK)

VIN0

VIN1

SVIN

VDD33

LOAD

SCL

SDA

ALERT

RUN0

RUN1

GPIO0

GPIO1

SYNC

SHARE_CLK

4.22k

±50ppm/°C

LTM4686B

4686B F35

SMBus INTERFACE WITH

PMBus COMMAND SET

ON/OFF CONTROL, FAULT

MANAGEMENT, POWER

SEQUENCING

11.3k

±50ppm/°C

VOUT0

TSNS0

VORB0+

VOSNS0+

VOSNS0–

VORB0–

VORB1

VOUT1

TSNS1a

TSNS1b

VOSNS1

SGND

Figure 35. 28A, 3.3V Output DC/DC µModule Regulator with Serial Interface

U1-LTM4686B-IOUT0

U1-LTM4686B-IOUT1

U2-LTM4650-IOUT1

U2-LTM4650-IOUT2

U3-LTM4650-IOUT1

U3-LTM4650-IOUT2

U4-LTM4650-IOUT1

U4-LTM4650-IOUT2

TOTAL OUTPUT CURRENT (A)

100 125 150 175

–3

4686B F34

LTM4686BIVPBF 数据表(PDF) 75 Page - Analog Devices

LTM4686BIVPBF 数据表(HTML) 75 Page - Analog Devices

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