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LTM4686BIVPBF 数据表(PDF) 73 Page - Analog Devices |
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LTM4686BIVPBF 数据表(HTML) 73 Page - Analog Devices |
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73 / 130 page  LTM4686B 73 Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS CIN1 10µF ×4 CIN5 150µF 10k ×7 VIN 4.5V TO 5.75V PWM CLOCK SYNCH. TIME BASE SYNCH. COUT(MLCC) 100µF ×10 COUT(BULK) 330µF ×10 VOUT, 1V ADJUSTABLE UP TO 108A (130A PEAK) VOUT0 TSNS0 VOSNS0+ VOSNS0– VINO VIN1 SVIN VDD33 LOAD SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP U1 LTM4686B + SMBus INTERFACE WITH PMBus COMMAND SET U1: SLAVE ADDRESS = 1000000_R/W (0x40) U2: SLAVE ADDRESS = 1000001_R/W (0x41) U3: SLAVE ADDRESS = 1000010_R/W (0x42) U4: SLAVE ADDRESS = 1000011_R/W (0x43) 750kHz SWITCHING FREQUENCY WITH INTERLEAVING NO GUI CONFIGURATION AND NO PART-SPECIFIC PROGRAMMING REQUIRED IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS IS RECOMMENDED ELECTRICALLY UNCONNECTED PINS VORB0+, VORB0– AND VORB1 NOT SHOWN SETTING MFR_PWM_CONFIG[7] = 1b, CONFIGURES THE VOUT1 CONTROL LOOP TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL- SENSE PIN-PAIR AS THE FEEDBACK SIGNAL FOR REGULATING VOUT1. ON/OFF CONTROL, FAULT MANAGEMENT, POWER SEQUENCING CIN2 10µF ×4 VOUT0 TSNS0 VOSNS0+ VOSNS0– VINO VIN1 SVIN VDD33 SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP 1.65k 1% ±50ppm/°C 787 1% ±50ppm/°C U2 LTM4686B 10.7k 1% ±50ppm/°C CIN3 10µF ×4 VOUT0 TSNS0 VOSNS0+ VOSNS0– VINO VIN1 SVIN VDD33 SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP 3.24k 1% ±50ppm/°C 1.65k 1% ±50ppm/°C U3 LTM4686B CIN4 10µF ×4 VOUT0 TSNS0 VOSNS0+ VOSNS0– VINO VIN1 SVIN VDD33 SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP 1.21k 1% ±50ppm/°C 4686B F32 CTHP 220pF CTH 3.3nF RTH 1.65k U4 LTM4686B VOUT1 TSNS1a TSNS1b VOSNS1 SGND VOUT1 TSNS1a TSNS1b VOSNS1 SGND VOUT1 TSNS1a TSNS1b VOSNS1 SGND VOUT1 TSNS1a TSNS1b VOSNS1 SGND Figure 32. Four Paralleled LTM4686B Producing 1VOUT at Up to 108A. Integrated Power System Management Features Accessible Over 2-Wire I2C/SMBus/PMBus Serial Interface. Evaluated on DC1989B-C, Custom-Stuffed with LTM4686B Modules |
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