LTM4686BIVPBF datasheet(14/130 Pages) AD

14 / 130 page

LTM4686B

Rev. 0

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PIN FUNCTIONS

this can be easily accomplished by connecting (an) R-C

network(s) from COMP0a and/or COMP1a—terminated

to SGND—and leaving COMP0b and/or COMP1b open,

as desired.

VOSNS0+ (D7): Channel 0 Positive Differential Voltage

Sense Input. Together, VOSNS0+ and VOSNS0– serve to

kelvin-sense the VOUT0 output voltage at VOUT0’s point

of load (POL) and provide the differential feedback signal

directly to Channel 0’s control loop and voltage super-

visor circuits. VOUT0 can regulate up to 3.6V output.

Command VOUT0’s target regulation voltage by serial bus.

Its initial command value at SVIN power-up is dictated

by NVM (nonvolatile memory) contents (factory default:

1.200V)—or, optionally, may be set by configuration

resistors; see VOUT0CFG, VTRIM0CFG and the Applications

Information section.

VORB0+ (D8): Channel 0 Positive Readback Pin. Shorted to

VOSNS0+ internal to the LTM4686B. If desired, place a test

point on this node and measure its impedance to VOUT0

on one’s hardware (e.g., motherboard, during in circuit

test (ICT) post-assembly process) to provide a means of

verifying the integrity of the feedback signal connection

between VOSNS0+ and VOUT0.

GPIO0, GPIO1 (E2 and F2, Respectively): Digital,

Programmable General Purpose Inputs and Outputs.

Open-drain outputs and/or high impedance inputs.

The LTM4686B’s factory-default NVM settings

for

MFR_GPIO_PROPAGATE

n—0x7993—and

MFR_GPIO_RESPONSEn—0x00—configure the GPIOn

pins to behave as conventional “power good” (PGOOD)

outputs for their respective channels. If PGOOD needs to

be valid in the interval between the application of SVIN and

NVM-to-RAM download completion (~32ms after SVIN is

applied): connect Schottky diodes between GPIOn and

RUNn, per Figure 1. In parallel applications, do not con-

nect GPIO0 to GPIO1 unless MFR_GPIO_RESPONSEn and

MFR_GPIO_PROPAGATEn are set accordingly. Pull-up

resistors from GPIOn to 3.3V are required for proper oper-

ation. See the Applications Information section for details.

ALERT (E3): Open-Drain Digital Output. A pull-up resistor

to 3.3V is required in the application only if SMBALERT

interrupt detection is implemented in one’s SMBus system.

SCL (E4): Serial Bus Clock Open-Drain Input (Can Be

an Input and Output, if Clock Stretching is Enabled). A

pull-up resistor to 3.3V is required in the application

for digital communication to the SMBus master(s) that

nominally drive this clock. The LTM4686B will never

encounter scenarios where it would need to engage clock

stretching unless SCL communication speeds exceed

100kHz—and even then, LTM4686B will not clock stretch

unless clock stretching is enabled by means of setting

MFR_CONFIG_ALL[1] = 1b. The factory-default NVM

configuration setting has MFR_CONFIG_ALL[1] = 0b:

clock stretching disabled. If communication on the bus at

clock speeds above 100kHz is required, the user’s SMBus

master(s) need to implement clock stretching support to

assure solid serial bus communications, and only then

should MFR_CONFIG_ALL[1] be set to 1b. When clock

stretching is enabled, SCL becomes a bidirectional, open-

drain output pin on LTM4686B.

SYNC (E5): PWM Clock Synchronization Input and Open-

Drain Output Pin. The setting of the FREQUENCY_SWITCH

command dictates whether the LTM4686B is a “sync

master” or “sync slave” module. When the LTM4686B is

a sync master, FREQUENCY_SWITCH contains the com-

manded switching frequency of Channels 0 and 1—in

PMBus linear data format—and it drives its SYNC pin low

for 500ns at a time, at this commanded rate. In contrast, a

sync slave uses MFR_CONFIG_ALL[4] = 1b and does not

pull its SYNC pin low. The LTM4686B’s PLL synchronizes

the LTM4686B’s PWM clock to the waveform present on

the SYNC pin—and therefore, a resistor pull-up to 3.3V

is required in the application, regardless of whether the

LTM4686B is a sync master or slave. EXCEPTION: driving

the SYNC pin with an external clock is permissible; see

the Applications Information section for details.

COMP0a, COMP1a (E6 and H6, Respectively): Current

Control Threshold and Error Amplifier Compensation

Nodes for Channels 0 and 1, Respectively. The trip thresh-

old of each channel’s current comparator increases with a

respective rise in COMPna voltage. Small filter capacitors

(22pF) internal to the LTM4686B on these COMP pins

LTM4686BIVPBF 数据表(PDF) 14 Page - Analog Devices

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