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LTM4686BIVPBF 数据表(PDF) 8 Page - Analog Devices |
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LTM4686BIVPBF 数据表(HTML) 8 Page - Analog Devices |
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8 / 130 page  LTM4686B 8 Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 5V, RUNn = 5V, FREQUENCY_SWITCH = 1MHz, VOUT_COMMANDn = 1V and VOUT_UV_FAULT_RESPONSEn = TON_MAX_FAULT_RESPONSEn = 0x00 unless otherwise noted. All other command codes configured per factory-default EEPROM settings unless otherwise noted. Tested per Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Temperature Readback for Channel 0, Channel 1, and Controller (Respectively: READ_TEMPERATURE_10, READ_TEMPERATURE_11, and READ_TEMPERATURE_2) TRES–RB Temperature Readback Resolution Channel 0, Channel 1, and Controller (Note 15) 0.0625 °C TRB–CH–ACC(72mV) Channel Temperature TUE, Switching Action Off Channels 0 and 1, PWM Inactive, RUNn = 0V, ∆VTSNSna = 72mV l Within ±3°C of Reading TRB–CH–ACC(ON) Channel Temperature TUE, Switching Action On READ_TEMPERATURE_1n, Channels 0 and 1, PWM Active, RUNn = 5V (Note 12) Within ±3°C of Reading TRB–CTRL–ACC(ON) Control IC Die Temperature TUE, Switching Action On READ_TEMPERATURE_2, PWM Active, RUN0 = RUN1 = 5V (Note 12) Within ±1°C of Reading, Typ tCONVERT–TEMP–RB Temperature Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x06 or 0x0A (Notes 9, 15) 90 8 ms ms VDD33 Regulator VVDD33 Internal VDD33 Voltage 3.2 3.3 3.4 V ILIM(VDD33) VDD33 Current Limit VDD33 Electrically Short-Circuited to GND 70 mA VVDD33_OV VDD33 Overvoltage Threshold (Note 15) 3.5 V VVDD33_UV VDD33 Undervoltage Threshold (Note 15) 3.1 V VDD25 Regulator VVDD25 Internal VDD25 Voltage 2.5 V ILIM(VDD25) VDD25 Current Limit VDD25 Electrically Short-Circuited to GND 50 mA Oscillator and Phase-Locked Loop (PLL) fOSC Oscillator Frequency Accuracy FREQUENCY_SWITCH = 1MHz (0x03E8) 500kHz ≤ FREQUENCY_SWITCH ≤ 1MHz (Note 15) l ±5 ±5 % % fSYNC PLL SYNC Capture Range (Note 16) l 450 1050 kHz VTH,SYNC SYNC Input Threshold VSYNC Rising (Note 15) VSYNC Falling (Note 15) 1.5 1 V V VOL,SYNC SYNC Low Output Voltage ISYNC = 3mA l 0.3 0.4 V ISYNC SYNC Leakage Current in Frequency Slave Mode 0V ≤ VSYNC ≤ 3.6V MFR_CONFIG_ALL[4] = 1b l ±5 µA θSYNC–θ0 SYNC-to-Channel 0 Phase Relationship, Lag from Falling Edge of Sync to Rising Edge of Top MOSFET (MT0) Gate (Note 15) MFR_PWM_CONFIG[2:0] = 000b, 01Xb MFR_PWM_CONFIG[2:0] = 101b MFR_PWM_CONFIG[2:0] = 001b MFR_PWM_CONFIG[2:0] = 1X0b 0 60 90 120 Deg Deg Deg Deg θSYNC–θ1 SYNC-to-Channel 1 Phase Relationship, Lag from Falling Edge of Sync to Rising Edge of Top MOSFET (MT1) Gate (Note 15) MFR_PWM_CONFIG[2:0] = 011b MFR_PWM_CONFIG[2:0] = 000b MFR_PWM_CONFIG[2:0] = 010b, 10Xb MFR_PWM_CONFIG[2:0] = 001b MFR_PWM_CONFIG[2:0] = 110b 120 180 240 270 300 Deg Deg Deg Deg Deg |
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