LTM4686BIVPBF datasheet(17/130 Pages) AD

17 / 130 page

LTM4686B

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

TSNS1a, TSNS1b (J3 and K3, Respectively): Channel 1

Temperature Excitation/Measurement and Thermal

Sensor Pins, Respectively. In most applications, con-

nect TSNS1a to TSNS1b. This allows the LTM4686B to

monitor the Power Stage Temperature of Channel 1. See

the Applications Information section for information on

how to use TSNS1a to monitor a temperature sensor

external to the module, e.g., a PN junction on the die of

a microprocessor.

VDD25 (J4): Internally Generated 2.5V Power Supply Output

Pin. Do not load this pin with external current; it is used

strictly to bias internal logic and provides current for the

internal pull-up resistors connected to the configuration-

programming pins. No external decoupling is required.

VDD33 (J5): Internally Generated 3.3V Power Supply

Output Pin. This pin should only be used to provide exter-

nal current for the pull-up resistors required for GPIOn,

SHARE_CLK, and SYNC, and may be used to provide

external current for pull-up resistors on RUNn, SDA, SCL

and ALERT. No external decoupling is required.

VORB1 (J7): Channel 1 Positive Readback Pin. Shorted to

VOSNS1 internal to the LTM4686B. At one’s option, place

a test point on this node and measure its impedance to

VOUT1 on one’s hardware (e.g., motherboard, during ICT

post-assembly process) to provide a means of verifying

the integrity of the feedback signal connection between

VOUT1 and VOSNS1.

VIN1 (J9, K9, L9, M9): Positive Power Input to Channel 1

Switching Stage. Provide sufficient decoupling capaci-

tance in the form of MLCCs and low ESR electrolytic (or

equivalent) to handle reflected input current ripple from the

step-down switching stage. MLCCs should be placed as

close to the LTM4686B as physically possible. See Layout

Recommendations in the Applications Information section.

WP (K4): Write Protect Pin, Active High. An inter-

nal 10μA current source pulls this pin to VDD33. If WP

is open circuit or logic high, only I2C writes to PAGE,

OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and

MFR_EE_UNLOCK are supported. Additionally, individual

faults can be cleared by writing 1b’s to bits of interest in

registers prefixed with “STATUS”. If WP is low, I2C writes

are unrestricted.

SW1 (L8): Switching Node of Channel 1 Step-Down

Converter Stage. Used for test purposes or EMI-snubbing.

May be routed a short distance to a local test point to moni-

tor switching action of Channel 1, if desired, but do not

route near any sensitive signals; otherwise, leave open.

LTM4686BIVPBF 数据表(PDF) 17 Page - Analog Devices

LTM4686BIVPBF 数据表(HTML) 17 Page - Analog Devices

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