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LTM4686BIVPBF 数据表(PDF) 32 Page - Analog Devices

部件名 LTM4686BIVPBF
功能描述  Ultrathin Dual 14A or Single 28A 關Module Regulator with Digital Power System Management
PDF  130 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTM4686BIVPBF 数据表(HTML) 32 Page - Analog Devices

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LTM4686B
32
Rev. 0
For more information www.analog.com
OPERATION
only I2C writes to the PAGE, OPERATION, CLEAR_FAULTS,
MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands
are supported, with the exception that individual fault bits
can be cleared by writing a “1b” to the respective bits in the
STATUS_* registers. Register reads are never restricted.
Not to be confused with the WP pin, the LTM4686B fea-
tures a WRITE_PROTECT register, which is also used to
restrict I2C writes to register contents. Refer to Appendix
C: PMBus Command Details for details. The WP pin and
the WRITE_PROTECT register provide a level of protection
against accidental changes to RAM and EEPROM contents.
The LTM4686B supports all possible 7-bit slave addresses.
The factory NVM-default slave address is 0x4F. The lower
four bits of the LTM4686B’s slave address can be altered
from this default value by connecting a resistor from
the ASEL pin to SGND. See Table 5 in the Applications
Information section for details. Bits[6:4] can be altered by
writing to the SLAVE_ADDRESS command. The value of
the SLAVE_ADDRESS command can be stored to NVM,
however, the lower four bits of the SLAVE_ADDRESS is
always dictated by the ASEL resistor pin-strap setting.
Up to four LTM4686B modules (8 channels) can be paral-
leled, suitable for powering ~108A loads such as CPUs
and GPUs. (See Figure 32) The LTM4686B can be par-
alleled with LTM4650 and other modules, as well (see
Figure 33 and Figure 34).
EEPROM
The LTM4686B’s control IC contains an internal EEPROM
(nonvolatile memory, NVM) with Error Correction Coding
(ECC) to store configuration settings and fault log informa-
tion. EEPROM endurance retention and mass write oper-
ation time are specified in the Electrical Characteristics
and Absolute Maximum Ratings sections. Write opera-
tions at TJ < 0°C or at TJ > 85°C are possible although
the Electrical Characteristics are not guaranteed and the
EEPROM retention characteristics may be degraded.
Read operations performed at junction temperatures
between –40°C and 125°C do not degrade the EEPROM.
The fault logging function, which is useful in debugging
system problems that may occur at high temperatures,
only writes to fault log-specific EEPROM locations (parti-
tions). If occasional writes to these registers occur above
85°C junction, the slight degradation in the data retention
characteristics of the fault log does not undermine the
usefulness of the function.
It is recommended that the EEPROM not be written when
the control IC die temperature is greater than 85°C. If the
die temperature exceeds 130°C, the LTM4686B’s control
IC disables all EEPROM write operations. EEPROM write
operations are subsequently re-enabled when the die tem-
perature drops below 125°C.
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using Equation 1.
AF
= e
Ea
k
⎝⎜
⎠⎟
1
TUSE+273
1
TSTRESS+273
⎝⎜
⎠⎟
(1)
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10–5 eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating
at a junction temperature of 130°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C
AF = e[(1.4/8.617 • 10–5) • (1/398 – 1/403)] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction tempera-
ture of 130°C for 10 hours. The effect of the overstress is
negligible when compared to the overall EEPROM reten-
tion rating of 87,600 hours at a maximum junction tem-
perature of 125°C.



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