LTM4686BIVPBF datasheet(69/130 Pages) AD

69 / 130 page

LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

EMI PERFORMANCE

The SWn pin provides access to the midpoint of the power

MOSFETs in LTM4686B’s power stages.

Connecting an optional series RC network from SWn to

GND can dampen high frequency (~30MHz+) switch node

ringing caused by parasitic inductances and capacitances

in the switched-current paths. The RC network is called

a snubber circuit because it dampens (or “snubs”) the

resonance of the parasitics, at the expense of higher

power loss.

To use a snubber, choose first how much power to allocate

to the task and how much PCB real estate is available to

implement the snubber. For example, if PCB space allows

a low inductance 1W resistor to be used—derated con-

servatively to 600mW (PSNUB)—then the capacitor in the

snubber network (CSW) is computed by Equation 10.

CSW =

PSNUB

VINn(MAX)2 • fSW

(10)

where VINn(MAX) is the maximum input voltage that the

input to the power stage (VINn) will see in the application,

and fSW is the DC/DC converter’s switching frequency

of operation. CSW should be NPO, C0G or X7R-type (or

better) material.

The snubber resistor (RSW) value is then given by

Equation 11.

RSW =

5nH

CSW

(11)

The snubber resistor should be low ESL and capable of

withstanding the pulsed currents present in snubber cir-

cuits. A value between 0.7Ω and 4.2Ω is normal.

SAFETY CONSIDERATIONS

The LTM4686B modules do not provide galvanic isolation

from VIN to VOUT. There is no internal fuse. If required,

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internal top MOSFET fault. If the internal top MOSFET fails,

then turning it off will not resolve the overvoltage, thus the

internal bottom MOSFET will turn on indefinitely trying

to protect the load. Under this fault condition, the input

voltage will source very large currents to ground through

the failed internal top MOSFET and enabled internal bot-

tom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can be

used as a secondary fault protector in this situation. The

device does support over current and overtemperature

protection.

LAYOUT CHECKLIST/EXAMPLE

The high integration of LTM4686B makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VINn, GND and VOUTn. It helps to minimize

the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VINn, GND and VOUTn pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath the

module.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

LTM4686BIVPBF 数据表(PDF) 69 Page - Analog Devices

LTM4686BIVPBF 数据表(HTML) 69 Page - Analog Devices

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