LTM4686BIVPBF datasheet(88/130 Pages) AD

88 / 130 page

LTM4686B

Rev. 0

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APPENDIX C: PMBUS COMMAND DETAILS

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the

SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part

must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and

a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications.

BIT

MEANING

EA Connection

0 – Independent EA and Channel Outputs

1 – EA1 uses EA0 input for PolyPhase operation

Reserved.

Reserved

Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until

SVIN > VIN_ON. The SHARE_CLK pin will be

pulled low when SVIN < VIN_OFF. If this bit is 0, the SHARE_CLK

pin will not be pulled low when SVIN < VIN_OFF except for the

initial application of SVIN.

Reserved

BIT [2:0]

CHANNEL 0 (DEGREES)

CHANNEL 1 (DEGREES)

000b

180

001b

270

010b

240

011b

120

100b

120

240

101b

240

110b

120

300

Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both COMPna pins

are tied together.

This command has one data byte.

FREQUENCY_SWITCH

The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device. See Table 7 for recom-

mended values.

Supported Frequencies:

VALUE [15:0]

RESULTING FREQUENCY (TYP)

0x0000

External Oscillator

0xFBE8

500kHz

0x023F

575kHz

0x028A

650kHz

0x02EE

750kHz

0x03E8

1000kHz

LTM4686BIVPBF 数据表(PDF) 88 Page - Analog Devices

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