LTM4686BIVPBF datasheet(15/130 Pages) AD

15 / 130 page

LTM4686B

Rev. 0

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PIN FUNCTIONS

(terminated to SGND) introduce high frequency roll off of

the error-amplifier response, yielding good noise rejection

in the control loop. See COMP0b/COMP1b.

VOSNS0– (E7): Channel 0 Negative Differential Voltage

Sense Input. See VOSNS0+.

VORB0– (E8): Channel 0 Negative Readback Pin. Shorted

to VOSNS0– internal to the LTM4686B. If desired, place

a test point on this node and measure its impedance to

GND on one’s hardware (e.g., motherboard, during ICT

post-assembly process) to provide a means of verifying

the integrity of the feedback signal connection between

VOSNS0– and GND (VOUT0 power return).

RUN0, RUN1 (F3 and F4, Respectively): Enable Run

Input for Channels 0 and 1, Respectively. Open-drain

input and output. Logic high on these pins enables the

respective outputs of the LTM4686B. These open-drain

output pins hold the pin low until the LTM4686B is out of

reset and SVIN is detected to exceed VIN_ON. A pull-up

resistor to 3.3V is required in the application. Do not pull

RUN logic high with a low impedance source.

SGND (F5–F6, G5–G6): Channel 1 Negative Voltage Sense

Input. See VOSNS1. Additionally, SGND is the signal ground

return path of the LTM4686B. If desired, one may place a test

point on one of the four SGND pins and measure its imped-

ance to GND on one’s hardware (e.g., motherboard, during

ICT post-assembly process) to provide a means of verify-

ing the integrity of the feedback signal connection between

the other three SGND pins and GND (VOUT1 power return).

SGND is not electrically connected to GND internal to the

LTM4686B. Connect SGND to GND local to the LTM4686B.

INTVCC (F7,G7):ControlCircuitandMOSFETDriverBiasPin.

Always connect to SVIN. No external decoupling is required.

SVIN (F9): Input Supply for LTM4686B’s Internal Control

IC. In most applications, SVIN connects to VIN0 and/or

VIN1, in which case no external decoupling beyond that

already allocated for VIN0/VIN1 is required. If SVIN is oper-

ated from an auxiliary supply separate from VIN0/VIN1,

decouple this pin to GND with a capacitor (0.1μF to 1μF).

ASEL (G2): Serial Bus Address Configuration Pin. On

any given I2C/SMBus serial bus segment, every device

must have its own unique slave address. If this pin is

left open, the LTM4686B powers up to a slave address

set by MFR_ADDRESS[6:0] (see Table 5). The factory-

default setting is 0x4F (hexadecimal), i.e., 1001111b

(industry standard convention is used throughout this

document: 7-bit slave addressing). The lower four bits of

the LTM4686B’s slave address can be altered from the

NVM-set value by connecting a resistor from this pin to

SGND. Minimize capacitance—especially when the pin is

left open—to assure accurate detection of the pin state.

VOUT0CFG (G3): Output Voltage Select Pin for VOUT0, Coarse

Setting. If the VOUT0CFG and VTRIM0CFG pins are both left

open—or, if the LTM4686B is configured to ignore pin-

strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] =

1b—then the LTM4686B’s target VOUT0 output voltage set-

ting (VOUT_COMMAND0) and associated power-good and

OV/UV warning and fault thresholds are dictated at SVIN

power-up according to the LTM4686B’s NVM contents.

A resistor* connected from this pin to SGND—in combi-

nation with resistor pin settings on VTRIM0CFG, and using

the factory-default NVM setting of MFR_CONFIG_ALL[6] =

0b—can be used to configure the LTM4686B’s Channel

0 output to power-up to a VOUT_COMMAND value (and

associated output voltage monitoring and protection/fault-

detection thresholds) different from those of NVM contents.

(See the Applications Information section.) Connecting

resistor(s) from VOUT0CFG to SGND and/or VTRIM0CFG to

SGND in this manner allows a convenient way to configure

multiple LTM4686Bs with identical NVM contents for dif-

ferent output voltage settings—all without GUI interven-

tion or the need to “custom-pre-program” module NVM

contents. Minimize capacitance—especially when the pin

is left open—to assure accurate detection of the pin state.

Note that use of RCONFIGs* on VOUT0CFG/VTRIM0CFG can

affect the VOUT0 range setting (MFR_PWM_MODE0[1])

and loop gain.

VOUT1CFG (G4): Output Voltage Select Pin for VOUT1,

Coarse Setting. If the VOUT1CFG and VTRIM1CFG pins are

both left open—or, if the LTM4686B is configured to

ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_

ALL[6] = 1b—then the LTM4686B’s target VOUT1 output

voltage setting (VOUT_COMMAND1) and associated OV/

*In applications where VOUT0 and VOUT1 are paralleled, the respective VOUTnCFG and VTRIMnCFG

pin-pairs can be electrically connected together; common RCONFIG resistors can be applied,

whose values are half of what is prescribed in Table 2 and Table 3. See Figure 35, for example.

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