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LTM4686BIVPBF 数据表(PDF) 78 Page - Analog Devices

部件名 LTM4686BIVPBF
功能描述  Ultrathin Dual 14A or Single 28A 關Module Regulator with Digital Power System Management
PDF  130 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTM4686BIVPBF 数据表(HTML) 78 Page - Analog Devices

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LTM4686B
78
Rev. 0
For more information www.analog.com
APPENDIX B
PMBUS SERIAL DIGITAL INTERFACE
The LTM4686B communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 37, shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The LTM4686B is a slave device. The master can com-
municate with the LTM4686B using the following formats:
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
The following PMBus protocols are supported:
n
Write Byte, Write Word, Send Byte, Block Write
n
Read Byte, Read Word, Block Read
n
Block Write – Block Read Process Call
n
Alert Response Address
Figure 39 to Figure 55 illustrate the aforementioned PMBus
protocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBus timeout may be extended when reading the fault log.
Figure 38 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n
Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
Figure 37. Timing Diagram
SDA
SCL
tHD(STA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tr
tf
tr
tf
tHIGH
4686B F37



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