LTM4686BIVPBF datasheet(63/130 Pages) AD

63 / 130 page

LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

joints and through a portion of the board. The board

temperature is measured a specified distance from the

package, using a two sided, two layer board. This board

is described in JESD51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal oper-

ating conditions of a µModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4686B, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to differ-

ent junctions of components or die are not exactly linear

with respect to total package power loss. To reconcile

this complication without sacrificing modeling simplic-

ity—but also not ignoring practical realities—an approach

has been taken using FEA software modeling along with

laboratory testing in a controlled-environment chamber

to reasonably define and correlate the thermal resistance

values supplied in this data sheet: (1) Initially, FEA software

is used to accurately build the mechanical geometry of

the LTM4686B and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-9 and

JESD51-12 to predict power loss heat flow and tempera-

ture readings at different interfaces that enable the cal-

culation of the JEDEC-defined thermal resistance values;

(3) the model and FEA software is used to evaluate the

LTM4686B with heat sink and airflow; (4) having solved

for and analyzed these thermal resistance values and simu-

lated various operating conditions in the software model,

a thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. The outcome of

this process and due diligence yields the set of derating

curves provided in later sections of this data sheet, along

with well-correlated JESD51-12-defined θ values provided

in the Pin Configuration section of this data sheet.

4686B F09

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

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