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LTM4686BIVPBF 数据表(PDF) 20 Page - Analog Devices |
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LTM4686BIVPBF 数据表(HTML) 20 Page - Analog Devices |
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20 / 130 page  LTM4686B 20 Rev. 0 For more information www.analog.com TEST CIRCUITS Test Circuit 1. LTM4686B ATE Single-Input-Supply Configuration, 4.5V ≤ VIN ≤ 5.75V Test Circuit 2. LTM4686B ATE Multi-Input-Supply Configuration, 2.375V ≤ VIN ≤ 5.75V CINH 10µF ×6 CINL 150µF VIN 4.5V TO 5.75V COUTH0 100µF ×4 VOUT0 1V ADJUSTABLE UP TO 14A (17A PEAK) VOUT1 1V ADJUSTABLE UP TO 14A (17A PEAK) VIN0 VIN1 SVIN VDD33 SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP VOUT0 TSNS0 VORB0+ VOSNS0+ VOSNS0– VORB0– VORB1 VOUT1 TSNS1a TSNS1b VOSNS1 SGND + COUTL0 OPT* + COUTL1 OPT* + LOAD0 COUTH1 100µF ×4 LTM4686B LOAD1 SMBus INTERFACE WITH PMBus COMMAND SET ON/OFF CONTROL, FAULT MANAGEMENT AND POWER SEQUENCING PWM CLOCK SYNCH TIME BASE SYNCH (PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN) RTH1 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING RTH0 30.1k 4686B TC01 CTH1 470pF CTH0 470pF RTH1 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING RTH0 30.1k CTH1 470pF CTH0 470pF CINH 10µF ×6 CINL 150µF VIN 2.375V TO 5.75V VIN_AUX 4.5V TO 5.75V 1µF COUTH0 100µF ×4 VOUT0 1V ADJUSTABLE UP TO 14A (17A PEAK) VOUT1 1V ADJUSTABLE UP TO 14A (17A PEAK) SVIN VIN0 VIN1 VDD33 SCL SDA ALERT RUN0 RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP + LOAD0 COUTH1 100µF ×4 LTM468B LOAD1 SMBus INTERFACE WITH PMBus COMMAND SET ON/OFF CONTROL, FAULT MANAGEMENT AND POWER SEQUENCING PWM CLOCK SYNCH TIME BASE SYNCH (PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN) 4686B TC02 COUTL0 OPT* + COUTL1 OPT* + VOUT0 TSNS0 VORB0+ VOSNS0+ VOSNS0– VORB0– VORB1 VOUT1 TSNS1a TSNS1b VOSNS1 SGND |
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