FXLS8971CF datasheet(23/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

aaa-040845

SCLK

tSET

tHOLD

tHZ

tSCS

tSCLK

tSCLKH

tSCLKL

tDDLY

tHCS

tWCS

High-Impedance

SPI_DATA

SPI_MISO

SPI_CS_B

Figure 16. SPI timing diagram (3-wire mode)

14 Operating modes

Mode[1]

I2C/SPI

bus state

VDD

Description

OFF

Unavailable

< 1.71 V

Communication with FXLS8971CF is not possible, but communications with other

devices on the same I2C/SPI bus is possible provided the VDD supply pin is left

floating/unconnected and not connected to GND.

If VDD is not left floating/unconnected, the ESD protection diodes on the interface

pins could become forward biased and clamp the bus, preventing normal

operation.

As soon as the supply reaches 1.71 V, the device BOOT process begins.

BOOT

Unavailable

≥ 1.71 V

BT_MODE = GND:

In this phase, the device is initialized and any default configuration parameters are

loaded from OTP memory. When this phase is complete, the SRC_BOOT bit is

set and a TPULSE-BOOT1 µs pulse may be signaled on either one of the INT1/2 pins

(defaults enabled on the INT1 pin after POR).

BT_MODE = VDD:

In this phase, the device is initialized and any default configuration parameters

are loaded from OTP memory, along with any default Motion Detection function

specific parameters. When the default configuration parameters are loaded from

OTP memory, the SRC_BOOT bit is set and a boot pulse, TPULSE-BOOT2, can be

signaled on the INT2 pin. By default, the boot pulse is routed to INT2 pin and

cannot be routed to INT1 pin.

Table 15. FXLS8971CF operating modes descriptions

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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