FXLS8971CF datasheet(40/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

BUF_WMRK

Buffer Watermark Event Flag:

0: The buffer watermark level programmed in BUF_CONFIG2[BUF_WMRK[5:0]] has not been

equaled or exceeded

1: The buffer watermark level programmed in BUF_CONFIG2[BUF_WMRK[5:0]] has been

equaled or exceeded.

This event flag may be cleared in one of the following ways:

1. The host must read out enough samples from the output buffer for

BUF_STATUS[BUF_

CNT[5:0]

] to go below the value set in BUF_CONFIG2[BUF_WMRK[5:0]].

2. The host must flush the buffer by setting

BUF_CONFIG2[BUF_FLUSH] = 1.

3. The host must set

BUF_CONFIG1[BUF_MODE[1:0]] = 00b to disable the buffer, which also

clears its contents.

The watermark interrupt may be used to enable an efficient DMA-based transfer of the buffer

contents to the host processor. For example, if the watermark level is set at 16 samples and

the interrupt is enabled and routed to one of the INT1 or INT2 pins, the event may be used

to trigger a single burst read operation of 1 (

BUF_STATUS) + (16 samples * 2 bytes/sample

* 3 (axes)) = 97 bytes to completely empty the buffer and clear the buffer status flags (when

SENS_CONFIG2[F_READ] = 0), or 49 bytes when SENS_CONFIG2[F_READ] = 1.

Note: Using a DMA operation to handle the burst read operation can allow the processor

to sleep or perform other tasks while the required number of samples is collected as a

background activity.

BUF_OVF

Buffer Overflow Event flag:

0: Buffer overflow event has not occurred. The number of samples stored in the buffer is less

than or equal to 32

1: Buffer overflow event has occurred

To clear this bit, the host must do one of the following:

1. At least one sample must be read in order to clear the BUF_OVF flag.

2. Flush the output buffer by setting

BUF_CONFIG2[BUF_FLUSH] = 1.

3. Disable the output buffer by setting

BUF_CONFIG1[BUF_MODE[1:0]] = 00b, which resets

BUF_STATUS[BUF_CNT[5:0]] to zero, but does not clear the buffer contents.

5 to 0

BUF_CNT[5:0]

This field contains the count of the number of acceleration data triplets (samples) currently

stored in the output data buffer (from 0-32). If the buffer is full (contains 32 samples), and an

additional data triplet is received, the count remains at 32, and the BUF_OVF event flag is

asserted.

Table 35. BUF_STATUS register (address 0Bh) bit description

15.2.7 BUF_X_LSB, BUF_X_MSB, BUF_Y_LSB, BUF_Y_MSB, BUF_Z_LSB, BUF_Z_MSB

(addresses 0Ch to 11h)

These registers contain either the buffer Head or Tail output acceleration sample data in 2's complement format.

The tail (oldest) sample is stored when the FIFO read out mode is selected, and the head (newest) sample is

stored when the LIFO read out mode is selected.

BUF_CONFIG1[BUF_TYPE] controls the read out mode.

The byte order of the output data is programmable via

SENS_CONFIG2[LE_BE], and defaults to little-endian

mode.

In little-endian mode, the output data buffer registers are arranged with the LSB of each axes data stored at the

lower address. The upper nibble (MSB) is stored at the next address, and is right justified. In little-endian mode,

the buffer output data is also sign extended to avoid the need for the host software to do sign extension of the

output data on a per sample (per axis) basis.

In big-endian mode (with

SENS_CONFIG2[LE_BE] = 1), the output buffer data registers are arranged with the

MSB of each axis data stored at the lower register address. The lower nibble(LSB) is stored at the next address,

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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