FXLS8971CF datasheet(61/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

01: Stream Mode: buffer always contains the most recent 32 samples when overflowed. The oldest

sample data is replaced with new data when the buffer becomes full and a new sample arrives.

10: Stop Mode: buffer stops accepting new samples when full.

11: Trigger mode: The buffer will operate in circular mode until the trigger event occurs, collecting

up to

BUF_CONFIG2[BUF_WMRK[5:0]] samples; after a configured trigger event occurs the buffer

continues to accept up to (32-

BUF_CONFIG2[BUF_WMRK[5:0]]) samples, set the BUF_OVF flag,

and stop collecting further samples. Trigger mode allows acceleration data to be collected both before

and after the trigger event, with the maximum number of pre-trigger samples defined by the

BUF_

CONFIG2[BUF_WMRK[5:0]] setting.

Note: The BUF_OVF flag is cleared and the triggered mode re-armed once the host flushes or reads

all the buffer contents.

The available trigger sources are the SDCD within- and outside-of-thresholds events, and orientation

change event. These trigger sources are enabled in this register via the TRIG_SDCD_WT, TRIG_

SDCD_OT, and TRIG_ORIENT bits.

BUF_GATE

Output data buffer gate enable:

0: Buffer gate is bypassed (default). Output data buffer is automatically flushed when FXLS8971CF

transitions from WAKE to SLEEP or SLEEP to WAKE modes. This operation prevents acceleration

data from two different ODRs rates becoming mixed in the output buffer.

1: The Output data buffer input gate is enabled when transitioning from WAKE to SLEEP or SLEEP to

WAKE modes; the entire buffer contents must be read out or flushed (

BUF_CONFIG2[BUF_FLUSH]

= 1) to allow the further collection of sample data. Any new samples that arrive before the buffer has

been read out or flushed are discarded, and the BUF_GATE_ERR bit in the

SYS_MODE register

is asserted.

SYS_MODE[BUF_GATE_CNT] maintains a count of the number of samples discarded

since the BUF_GATE_ERR flag was asserted.

Although FXLS8971CF still transitions from WAKE to SLEEP or SLEEP to WAKE, the contents of

the FIFO buffer are preserved, and any new data samples are not stored in the buffer until it is either

emptied of flushed by the host application.

Notes:

• The BUF_GATE_ERR flag remains asserted as long as the buffer remains un-emptied.

• When triggered buffer mode (BUF_MODE = 11b) is selected and ASLP_COUNT ≥ 1, the BUF_

GATE setting is ignored.

• The BUF_GATE bit in 1: Trigger source is enabled, when set, holds the last data set stored in the

buffer before transitioning to the SLEEP or WAKE modes. After the buffer is flushed, FXLS8971CF

will start accepting new sample data into the buffer at the current operating mode ODR.

TRIG_SDCD_WT

SDCD within thresholds event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

TRIG_SDCD_OT

SDCD outside of thresholds event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

TRIG_ORIENT

Orientation change event buffer trigger enable:

0: Trigger source is disabled (default).

1: Trigger source is enabled

Table 79. BUF_CONFIG1 register (address 26h) bit description...continued

The buffer contents are flushed whenever the buffer is disabled (by setting BUF_MODE = 00b), when

BUF_CONFIG2[BUF_FLUSH] is set, or after an automatic power mode change when transitioning from

WAKE-to-SLEEP or SLEEP-to-WAKE with

BUF_CONFIG1[BUF_GATE] = 0. The buffer contents are also

automatically flushed on a transition from STANDBY to ACTIVE or STANDBY to EXT_TRIG mode. The buffer

may be prevented from being flushed when transitioning from WAKE-to-SLEEP or SLEEP-to-WAKE by setting

BUF_CONFIG1[BUF_GATE] = 1.

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

61 / 100

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