FXLS8971CF datasheet(36/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

15.2.2 TEMP_OUT register (address 01h)

Bit

Name

TEMP_OUT[7:0]

Reset

—

Access

Table 23. TEMP_OUT register (address 01h) bit allocation

The

TEMP_OUT register contains the 8-bit, 2's complement temperature value. When this register contains the

value 00h, the measured temperature is 25 °C (typ). This register is updated on every ODR cycle.

15.2.3 VECM_LSB register (address 02h)

This register contains the LSB of the 12-bit, unsigned vector magnitude result (acceleration vector modulus);

The result is only calculated when

SENS_CONFIG5[VECM_EN] = 1.

Note: Whenever the VECM_LSB or VECM_MSB registers are read the SRC_DRDY event flag is also cleared.

The byte order of the vector magnitude output data is programmable via SENS_CONFIG2[LE_BE] and defaults

to little-endian mode.

Bit

Name

VECM[7:0]

Reset

Access

Table 24. VECM_LSB register (address 02h) bit allocation

Field

Description

7 to 0

VECM[7:0]

LSB of the 12-bit unsigned acceleration vector modulus result

Table 25. VECM_LSB register (address 02h) bit description

15.2.4 VECM_MSB register (address 03h)

This register contains the MSB of the 12-bit, unsigned vector magnitude result (acceleration vector modulus);

The result is only calculated when

SENS_CONFIG5[VECM_EN] = 1.

Note: Whenever the VECM_LSB or VECM_MSB registers are read the SRC_DRDY event flag is also cleared.

The byte order of the vector magnitude output data is programmable via

SENS_CONFIG2[LE_BE] and defaults

to little-endian mode.

Bit

Name

—

VECM[11:8]

Reset

Access

Table 26. VECM_MSB register (address 03h) bit allocation

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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