FXLS8971CF datasheet(45/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

is received, SYS_MODE[1:0] is set to 01b while the measurement is being made, and then

change back to 11b and remain there until the next trigger signal is received.

• When INT_EN[WAKE_OUT_EN] = 1, and SYS_MODE[1:0] = 01b (WAKE), the device outputs

either a logic '1' or '0' on either the INT1 or INT2 pins, depending on the settings made in

INT_

PIN_SEL[WAKE_OUT_INT2] and SENS_CONFIG4[INT_POL].

• When entering the WAKE, SLEEP, or EXT_TRIG modes, the internal debounce counters for

the ORIENT, SDCD_WT, and SDCD_OT event functions are automatically reset.

Table 46. SYS_MODE register (address 14h) bit description...continued

15.3 Sensor main configuration registers

15.3.1 SENS_CONFIG1 register (address 15h)

Bit

Name

RST

ST_AXIS_SEL[1:0]

ST_POL

SPI_M

FSR[1:0]

ACTIVE

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 47. SENS_CONFIG1 register (address 15h) bit allocation

Field

Description

RST

The RST bit may be used to initiate a software reset. The reset mechanism can be triggered in

Standby, Active (WAKE or SLEEP), and EXT_TRIG operating modes. When the RST bit is set, the

boot mechanism resets all functional blocks and loads the internal registers with their default values

(The

INT_POL, INT_PP_OD, and BOOT_DIS bits are not reset and maintains their current values

as long as power is not removed from the VDD pin and Hibernate mode is not enabled). The host

application should allow TBOOT1 or TBOOT2 ms between issuing a reset command and attempting

communications with FXLS8971CF over the I2C/SPI interfaces. Alternatively, the host can wait for the

active edge on the TBOOT1/2 pulse event signaled on the configured INTx pin.

0: No device reset pending

1: Write '1' to trigger the soft reset sequence

Notes:

• The I2C and SPI interface blocks are also reset to avoid corrupted data transactions.

• The reset sequence does not start until the host I2C controller issues the SP (stop) condition, or the

SPI primary releases the SPI_CS_B pin.

• The host always reads back this bit as '0'.

• There is a delay of 300 μs to 500 μs between setting the RST bit and the commencement of the

reset sequence.

6 to 5

ST_AXIS_SEL[1:0]

Self-test axis selection

This bit field selects the transducer axis to test using the Self-Test function. The ST_POL bit allows

either positive or negative self-test displacements to be applied.

The host system may use the self-test function to verify the functionality of both the transducer and

signal measurement chain without the need to apply an external acceleration stimulus.

Notes:

• The data output from the two axes that are not selected by ST_AXIS_SEL during the self-test

sequence are not meaningful and should be ignored.

Table 48. SENS_CONFIG1 register (address 15h) bit description

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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