FXLS8971CF datasheet(41/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

and is left justified. The lower 4 bits of the LSB are always read as '0'. The host software must right shift the data

by 4 bits (or divide the value by 16) in order to obtain the correct scaling of the acceleration data.

SENS_CONFIG2[F_READ] = 1, the auto increment mechanism skips over the MSB registers. This operation

shortens the output data size from 6 bytes to 3 bytes per XYZ sample. When

SENS_CONFIG2[F_READ]

= 1, the MSB of each axes data is stored at the LSB address, regardless of the setting made in

SENS_CONFIG2[LE_BE]. The output data size may also be reduced using the X/Y/Z_DIS bits located in the

SENS_CONFIG5 register. These bits can be used to selectively disable each axis from being read out using the

auto-increment mechanism. For example, setting X_DIS causes the auto-increment mechanism to skip over the

BUF_X LSB and MSB registers, thereby shortening the number of bytes to be read from 6 to 4, or from 3 to 2

when F_READ = 1.

Note: Reading the BUF_STATUS register is not required in order to clear the BUF_WMRK event flag - if the

host has mapped more than the BUF_WMRK event flag to the same interrupt pin, the

BUF_STATUS register

should be used to confirm that a BUF_WMRK event was the source of the interrupt before initiating the burst

read operation.

Bit

Name

BUF_X[7:0]

Reset

—

Access

Table 36. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

BUF_X[11:8]

Reset

—

Access

Bit

Name

BUF_Y[7:0]

Reset

—

Access

Table 37. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

BUF_Y[11:8]

Reset

—

Access

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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