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FXLS8971CF 数据表(PDF) 50 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 50 Page - NXP Semiconductors |
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50 / 100 page ![]() NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer DEC[3] DEC[2] DEC[1] DEC[0] Decimation selection (samples) Measurement time (ms) 0 0 0 0 1 0.3125 0 0 0 1 2 0.625 0 0 1 0 4 1.25 0 0 1 1 8 2.5 0 1 0 0 16 5 0 1 0 1 32 10 0 1 1 0 64 20 0 1 1 1 128 40 1 0 0 0 256 80 1 0 0 1 512 160 1 0 1 0 1024 320 1 0 1 1 2048 640 1 1 0 0 4096 1280 1 1 0 1 4096 1280 1 1 1 0 4096 1280 1 1 1 1 4096 1280 Table 54. WAKE and SLEEP decimation settings in Flexible Power mode 15.3.4 SENS_CONFIG4 register (address 18h) Bit 7 6 5 4 3 2 1 0 Name EXT_ TRIG_M WAKE_ SDCD_WT WAKE_ SDCD_OT WAKE_ ORIENT DRDY_PUL INT2_FUNC INT_ PP_OD INT_POL Reset 0 0 0 0 0 0 0 1 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 55. SENS_CONFIG4 register (address 18h) bit allocation Field Description 7 EXT_TRIG_M External trigger function acquisition mode. 0 (default): Each positive going trigger edge causes a single ADC acquisition to be made. When the number of acquisitions specified by the current operating mode decimation setting have been triggered, the final decimated output is stored in the OUT_X/Y/Z registers or the buffer depending on the setting made in BUF_CONFIG1[BUF_MODE[1:0]]. . 1: Each positive going trigger edge causes multiple ADC acquisitions. The number of acquisitions are specified by the current operating mode decimation setting[1]. Once the specified number of acquisitions have been made, the final decimated output is stored in the OUT_X/Y/Z registers or the buffer depending on the setting made in BUF_CONFIG1[BUF_MODE[1:0]]. Notes: • The EXT_TRIG_M setting only applies when INT2_FUNC = 1. Table 56. SENS_CONFIG4 register (address 18h) bit description FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 50 / 100 |
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