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FXLS8971CF 数据表(PDF) 33 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 33 Page - NXP Semiconductors |
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33 / 100 page  NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer Auto-increment Address Name Type Register Address F_READ = 0 F_READ = 1 Default Values BT_MODE = GND/[VDD] Comment SDCD_LTHS_LSB [1] [5] R/W 33h 34h 00h/[C0h] Sensor Data Change Detection lower threshold value LSB - sdcd_lths[7:0] SDCD_LTHS_MSB [1] [5] R/W 34h 35h 00h/[0Fh] Sensor Data Change Detection lower threshold value MSB - sdcd_lths[11:8]. SDCD_UTHS_LSB [1] [5] R/W 35h 36h 00h/[40h] Sensor Data Change Detection upper threshold value LSB - sdcd_uths[7:0] SDCD_UTHS_MSB [1] [5] R/W 36h 37h 00h/[00h] Sensor Data Change Detection upper threshold value MSB - sdcd_uths[11:8] SELF_TEST_CONFIG1 [1] [5] R/W 37h 38h 00h Self-Test Idle phase duration: SELF_TEST_CONFIG2 [1] [5] R/W 38h 39h 00h Self-Test measurement phase decimation factor reserved register 12 R/W 39h 3Ah 00h Factory reserved register; do not modify reserved register 13[1] R 3Ah 00h — Factory reserved register Table 20. Register address map...continued [1] Register contents are preserved when a transition from ACTIVE to STANDBY mode occurs. All register contents are lost when a transition from Hibernate mode or a POR/BOR event occurs. [2] Register contents are reset when a transition from STANDBY to ACTIVE or EXT_TRIG mode occurs. [3] The byte order and L/R justification of these registers is user programmable between little-endian right justified and big-endian (left justified) modes. The default mode is little-endian, right justified. The byte order and justification is controlled by SENS_CONFIG3[LE_BE]. [4] The output data buffer contents become obsolete whenever a transition from STANDBY-to-ACTIVE or STANDBY-to-EXT_TRIG modes occurs. [5] Register contents can only be modified while the device is in STANDBY mode; the only exceptions are the SENS_CONFIG1[ACTIVE], SENS_ CONFIG1[RST] and BUF_CONFIG1[BUF_FLUSH] bits that may be set at any time in STANDBY, ACTIVE, or EXT_TRIG modes. The ACTIVE bit state cannot be modified while in EXT_TRIG operating mode. 15.2 Data and status read registers 15.2.1 INT_STATUS register (address 00h) Bit 7 6 5 4 3 2 1 0 Name SRC_DRDY SRC_OVF SRC_BUF SRC_ SDCD_OT SRC_ SDCD_WT SRC_ ORIENT SRC_ASLP SRC_BOOT Reset 0 0 0 0 0 0 0 1 Access R R R R R R R R Table 21. INT_STATUS register (address 00h) bit allocation FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 33 / 100 |
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