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FXLS8971CF 数据表(PDF) 57 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 57 Page - NXP Semiconductors |
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57 / 100 page  NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer • The INT2/BOOT_OUT pin only signals the boot process complete interrupt, signaled by a TPULSE-BOOT2 ms active low pulse (open-drain with external pull-up). Any other interrupt sources mapped to the INT2/ BOOT_OUT pin are ignored. Bit 7 6 5 4 3 2 1 0 Name DRDY_EN BUF_EN SDCD_ OT_EN SDCD_ WT_EN ORIENT_ EN ASLP_EN BOOT_ DIS WAKE_ OUT_EN Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 1 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 71. INT_EN register (address 20h) bit allocation Field Description 7 DRDY_EN Data-ready interrupt output enable 0 (default): Interrupt is disabled. 1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as configured by the setting made in INT_PIN_SEL. Note: When BT_MODE = GND, SRC_DRDY bit and the signaled interrupt are cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read. When BT_MODE = VDD, SRC_DRDY bit is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read. However the data ready interrupt is signaled for TPULSE-MOT s (5 ms typ) and it clears itself automatically. The current data ready interrupt pulse is terminated when the device transitions into STANDBY mode before its completion and therefore may not span for entire TPULSE-MOTs. 6 BUF_EN Output data buffer interrupt output enable 0 Interrupt is not routed to the INTx output pins (default) 1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in INT_ PIN_SEL. 5 SDCD_OT_EN SDCD outside of thresholds interrupt output enable 0 (default): Interrupt is disabled. 1: Interrupt is routed to either the INT1 or INT2 output pin as configured by the setting made in INT_ PIN_SEL. 4 SDCD_WT_EN SDCD within thresholds interrupt output enable 0 (default): Interrupt is disabled. 1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in INT_ PIN_SEL. 3 ORIENT_EN Orientation interrupt output enable 0 (default): Interrupt is disabled. 1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the setting made in INT_PIN_SEL. 2 ASLP_EN Auto-WAKE/SLEEP interrupt output enable 0 (default): Interrupt is disabled. 1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the setting made in INT_PIN_SEL. 1 BOOT_DIS Boot interrupt output disable 0 (default): Boot interrupt is enabled and routed to either the INT1 or INT2 output pin as determined by the setting made in INT_PIN_SEL. This interrupt is pulsed, with the polarity of the pulse determined by the setting made in SENS_CONFIG4[INT_POL]. Table 72. INT_EN register (address 20h) bit description FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 57 / 100 |
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