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FXLS8971CF 数据表(PDF) 52 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 52 Page - NXP Semiconductors |
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52 / 100 page  NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer Field Description • The INT_PP_OD bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/ BOOT_OUT output driver type is fixed to open-drain. 0 INT_POL Interrupt logic polarity on INT1 and INT2 pins Selects the polarity of the interrupt output signal on the INT1 and INT2 pins. 0: Active low: interrupt events are signaled with a logical '0' level. If DRDY_PUL=1, a SRC_DRDY event pulse is negative going. The inactive state of the INTx pins is logic '1' (VDD). 1 (default): Active high: interrupt events are signaled with a logical '1' level. If DRDY_PUL=1, a SRC_ DRDY event pulse is positive going. The inactive state of the INTx pins is logic '0' (GND). Notes: • If a user operation sets INT_POL before issuing a soft reset command, the setting is maintained through the reset sequence (only lost if VDD supply is removed or Hibernate mode is enabled). • The INT_POL bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/ BOOT_OUT interrupt logic polarity is fixed at active low (external pull-up resistors are required). Table 56. SENS_CONFIG4 register (address 18h) bit description...continued [1] In order to acquire all the measurements specified by the decimation setting, only one trigger event is needed. INTx pin configuration INT_PP_OD INT_POL INTx pin asserted value INTx pin deasserted value CMOS output 0 0 0 1 CMOS output 0 1 1 0 External pull-up resistor added (open-drain) 1 0 0 High-Z[1] External pull-down resistor added (open source) 1 1 1 High-Z[1] Table 57. INTx pin behavior as a function of INT_PP_OD and INT_POL bit settings (valid only when BT_MODE = VDD) [1] High-Z means high impedance condition, with the state of the INTx pin defined by the external pull-up or pull-down resistor. INTx pin configuration INT_PP_OD INT_POL INTx pin asserted value INTx pin deasserted value External pull-up resistor added (open-drain) X X 0 1 Table 58. INTx pin behavior as a function of INT_PP_OD and INT_POL bit settings (valid only when BT_MODE = VDD) 15.3.5 SENS_CONFIG5 register (address 19h) Bit 7 6 5 4 3 2 1 0 Name — — — VECM_EN X_DIS Y_DIS Z_DIS HIBERNATE_ EN Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 59. SENS_CONFIG5 register (address 19h) bit allocation FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 52 / 100 |
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