FXLS8971CF datasheet(73/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

10b: The function updates the SDCD_REF_X/Y/Z values with the current decimated and trimmed X/

Y/Z acceleration input data after the function evaluation. This operation allows for acceleration slope

detection with Data(n) to Data(n–1) always used as the input to the window comparator.

11b: The function uses a fixed value of 0 for each of the SDCD_REF_X/Y/Z registers, making the

function operate in absolute comparison mode.

OT_DBCTM

SDCD outside-of-threshold event debounce counter behavior

0 (default): Debounce counter decrements by 1 when the current outside of thresholds result for the

enabled axes is false. In this mode, the debounce counter de-bounces the outside of thresholds event

in both directions, meaning that once the event flag has been set (after SDCD_OT_DBCNT ODR

periods with the condition true), the condition must also remain false for at least SDCD_OT_DBCNT +

1 consecutive ODR periods before the next event detection cycle can begin.

1: Debounce counter is cleared whenever the current outside of thresholds result for the enabled

axes is false.

WT_DBCTM

SDCD within-thresholds event debounce counter behavior

0 (default): Debounce counter decrements by 1 when the current within thresholds result for the

enabled axes is false. In this mode, the debounce counter de-bounces the event in both directions,

meaning that once the event flag has been set (after SDCD_WT_DBCNT ODR periods with the

condition true), the condition must also remain false for at least SDCD_WT_DBCNT + 1 consecutive

ODR periods before the next event detection cycle can begin.

1: Debounce counter is cleared whenever the SDCD within thresholds result for the enabled axes is

false.

WT_LOG_SEL

SDCD within-thresholds event logic selection

0 (default): Function uses the logical AND of the enabled axes.

1: Function uses the logical OR of the enabled axes.

MODE

SDCD input data mode

0 (default): Function uses X, Y, Z acceleration data for the window comparison.

1: Function uses Vector magnitude data for the window comparison on the X-axis channel only; all

other SDCD channels are disabled and ignored by the function.

Note: The SENS_CONFIG5[VECM_EN] bit must also be set in order for the SDCD function to

operate correctly when MODE is set to 1.

REF_UPD

SDCD synchronous X/Y/Z reference values update bit

0: No reference update pending or reference update has completed.

1: Triggers a synchronous update of the internal X/Y/Z reference registers.

When the REF_UPD bit is set, it forces a synchronous update of the internal REF_X/Y/Z registers. If

REF_UPDM[1:0] = 11b (absolute mode), no update occurs and the REF_X/Y/Z values remain fixed

at 000h. The actual update of the internal reference values with the X/Y/Z acceleration data may be

delayed by up to 1 ODR period after this bit is set. See Figure 21 for further details.

Notes:

• This bit is self-cleared after the REF_X/Y/Z registers are updated. The host may not be able to

observe a value of '1' as the operation can complete before the next I2C or SPI read cycle occurs.

• This bit can be written at any time in either Active or Standby mode.

Table 103. SDCD_CONFIG2 register (address 30h) bit description...continued

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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