FXLS8971CF datasheet(76/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

The scaling for this register is always the same as the selected FSR sensitivity. See Section 9 for the sensitivity

values corresponding to each of the selectable FSRs.

Bit

Name

—

SDCD_LTHS[11:8]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 110. SDCD_LTHS_MSB register (address 34h) bit allocation

Field

Description

3 to 0

SDCD_LTHS[11:8]

MSB (nibble) of the signed 12-bit 2's complement lower-threshold value

Table 111. SDCD_LTHS_MSB register (address 34h) bit description

15.5.9 SDCD_UTHS_LSB register (address 35h)

Sensor Data Change Detection function 12-bit 2's complement upper-threshold least significant byte.

SDCD_UTHS[11:0] must always be set to a higher value than SDCD_LTHS[11:0] to ensure that the SDCD

circuit functions correctly and produces meaningful results.

The scaling for this register is the same as the selected FSR sensitivity. See Section 9 for the sensitivity values

corresponding to each of the selectable FSRs.

Bit

Name

SDCD_UTHS[7:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 112. SDCD_UTHS_LSB register (address 35h) bit allocation

Field

Description

7 to 0

SDCD_UTHS[7:0]

LSB of the signed 12 bit 2's complement upper-threshold value

Table 113. SDCD_UTHS_LSB register (address 35h) bit description

15.5.10 SDCD_UTHS_MSB register (address 36h)

Sensor Data Change Detection function 12-bit 2's complement upper-threshold most-significant byte (nibble).

SDCD_UTHS[11:0] must always be set to a higher value than SDCD_LTHS[11:0] to ensure that the SDCD

circuit functions correctly and produces meaningful results.

The scaling for this register is always the same as the selected FSR sensitivity. See Section 9 for the sensitivity

values corresponding to each of the selectable FSRs.

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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