FXLS8971CF datasheet(47/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

7 to 6

WAKE_PM[1:0]

WAKE power mode selection

00b: Low-power mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as WAKE_ODR[3:0]

and sets the ODR and decimation factor as per Table 52.

01b: High performance mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as WAKE_

ODR[3:0] and set the ODR and decimation factor as per Table 53.

1xb: Flexible performance mode is selected;

SENS_CONFIG3[7:4] bits are interpreted as WAKE_

DEC[3:0], which sets the measurement decimation factor. The effective ODR (and measurement

current) is determined by the combination of the decimation factor and the 12-bit measurement idle

time programmed in the

WAKE_IDLE_MSB and WAKE_IDLE_LSB registers. See Table 54 for the

selectable decimation factors.

Note: In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only

the default LPM mode should be used.

5 to 4

SLEEP_PM[1:0]

SLEEP power mode selection

00b: Low-power mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as SLEEP_ODR[3:0]

and sets the ODR and decimation factor as per Table 52.

01b: High performance mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as SLEEP_

ODR[3:0] and set the ODR and decimation factor as per Table 53.

1xb: Flexible performance mode is selected;

SENS_CONFIG3[3:0] bits are interpreted as SLEEP_

DEC[3:0], which sets the measurement decimation factor. The effective ODR (and measurement

current) is determined by the combination of the decimation factor and the 12-bit measurement idle

time programmed in the

SLEEP_IDLE_MSB and SLEEP_IDLE_LSB registers. See Table 54 for the

selectable decimation factors.

Note: In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only

the default LPM mode should be used.

LE_BE

Little/Big-endian output mode selection

0: Little-endian output mode is selected; the output data LSBs are stored at the lower logical address

and the MSBs (nibbles) are right-justified.

1: Big-endian output mode is selected; the output data MSBs are stored at the lower logical address

and the LSBs (nibbles) are left justified.

Note: The output data format selection applies only to the data read from the OUT_X/Y/Z, VECM,

and

BUF_X/Y/Z registers. All other multi-byte fields within the device are fixed in little-endian right

justified format.

AINC_TEMP

Temperature output data auto-increment control

0 (default):

TEMP_OUT register content is not included in auto-increment address range.

TEMP_OUT register content is included in auto-increment address range.

F_READ

Fast-read mode selection

When this bit is set, the output data format is limited to the most significant byte of the 12-bit sample.

The MSB data is always stored in the lower address, regardless of the setting made in

SENS_

CONFIG1[LE_BE]. The auto-increment address pointer automatically skips over the higher address

for each axis' sample when performing a burst read operation of the current output data or buffered

data when the F_READ bit is set.

0: Normal read mode

1: Fast-read mode

Table 50. SENS_CONFIG2 register (address 16h) bit description

15.3.3 SENS_CONFIG3 register (address 17h)

The SENS_CONFIG3 register is used to set the WAKE and SLEEP ODRs when operating in low-power mode

or High Performance Mode, and the decimation factor for WAKE and SLEEP modes in Flexible Power Mode.

Notes:

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

47 / 100

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