FXLS8971CF datasheet(82/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

16.4 Power supply considerations

NXP recommends that VDD be sourced from a low noise linear supply regulator (LDO). When using a switch

mode supply, the recommended minimum voltage is 1.8 V (nominal), providing headroom for supply noise

and ripple rejection. This headroom ensures that the device meets its performance specifications while also

preventing a BOR/POR event from occurring when operated on a noisy supply rail.

FXLS8971CF contains a POR generator. This circuit resets the digital logic and restores all register content to

the default values shown in Table 20 after applying VDD ≥ 1.71 V, or after a soft reset command is issued by

setting

SENS_CONFIG1[RST] = 1.

Note: The host system must wait for a nominal time period of TBOOT1/2 ms after applying VDD ≥ 1.71 V, or after

issuing a soft reset command, to allow enough time for FXLS8971CF to complete its internal boot sequence

and be ready for communication over the I2C or SPI interfaces.

When the BT_MODE pin is low, with

INT_EN[BOOT_DIS] = 0, the host system can wait until the active edge

of a TPULSE-BOOT1 µs pulse is observed on the INTx pin (determined by INT_PIN_SEL[BOOT_INT2]) indicating

completion of the boot sequence. When the BT_MODE pin is logic high, the INT2 pin is configured as an open-

drain output (BOOT_OUT) that pulses low for TPULSE-BOOT2 ms after the boot sequence completes.

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

82 / 100

FXLS8971CF 数据表(PDF) 82 Page - NXP Semiconductors