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FXLS8971CF 数据表(PDF) 97 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 97 Page - NXP Semiconductors |
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97 / 100 page ![]() NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer Tab. 56. SENS_CONFIG4 register (address 18h) bit description ....................................................... 50 Tab. 57. INTx pin behavior as a function of INT_PP_ OD and INT_POL bit settings (valid only when BT_MODE = VDD) ................................ 52 Tab. 58. INTx pin behavior as a function of INT_PP_ OD and INT_POL bit settings (valid only when BT_MODE = VDD) ................................ 52 Tab. 59. SENS_CONFIG5 register (address 19h) bit allocation ......................................................... 52 Tab. 60. SENS_CONFIG5 register (address 19h) bit description ....................................................... 53 Tab. 61. WAKE_IDLE_LSB register (address 1Ah) bit allocation .................................................... 54 Tab. 62. WAKE_IDLE_MSB register (address 1Bh) bit allocation .................................................... 54 Tab. 63. SLEEP_IDLE_LSB register (address 1Ch) bit allocation .................................................... 54 Tab. 64. SLEEP_IDLE_MSB register (address 1Dh) bit allocation .................................................... 54 Tab. 65. ASLP_COUNT_LSB register (address 1Eh) bit allocation .................................................... 55 Tab. 66. ASLP_COUNT_LSB register (address 1Eh) bit description .................................................. 55 Tab. 67. ASLP_COUNT_MSB register (address 1Fh) bit allocation ............................................55 Tab. 68. ASLP_COUNT_MSB register (address 1Fh) bit description ......................................... 55 Tab. 69. ASLP_COUNT timer period ............................ 56 Tab. 70. Auto-WAKE/SLEEP Interrupt Event Sources ........................................................... 56 Tab. 71. INT_EN register (address 20h) bit allocation ......................................................... 57 Tab. 72. INT_EN register (address 20h) bit description ....................................................... 57 Tab. 73. INT_PIN_SEL register (address 21h) bit allocation ......................................................... 58 Tab. 74. INT_PIN_SEL register (address 21h) bit description ....................................................... 58 Tab. 75. OFF_X register (addresses 22h) bit allocation ......................................................... 60 Tab. 76. OFF_Y register (addresses 23h) bit allocation ......................................................... 60 Tab. 77. OFF_Z register (addresses 24h) bit allocation ......................................................... 60 Tab. 78. BUF_CONFIG1 register (address 26h) bit allocation ......................................................... 60 Tab. 79. BUF_CONFIG1 register (address 26h) bit description ....................................................... 60 Tab. 80. BUF_CONFIG2 register (address 27h) bit allocation ......................................................... 62 Tab. 81. BUF_CONFIG2 register (address 27h) bit description ....................................................... 62 Tab. 82. ORIENT_STATUS register (address 28h) bit allocation .................................................... 63 Tab. 83. ORIENT_STATUS register (address 28h) bit description .................................................. 63 Tab. 84. ORIENT_CONFIG register (address 29h) bit allocation .................................................... 64 Tab. 85. ORIENT_CONFIG register (address 29h) bit description .................................................. 64 Tab. 86. ORIENT_DBCOUNT register (address 2Ah) bit allocation ........................................... 65 Tab. 87. ORIENT_DBCOUNT register (address 2Ah) bit description ......................................... 65 Tab. 88. ORIENT_BF_ZCOMP register (address 2Bh) bit allocation ........................................... 65 Tab. 89. ORIENT_BF_ZCOMP register (address 2Bh) bit description ......................................... 65 Tab. 90. ORIENT_ZLOCK lockout angles .....................65 Tab. 91. ORIENT Back/Front orientation transition angle definitions .............................................. 66 Tab. 92. ORIENT_THS register (address 2Ch) bit allocation ......................................................... 66 Tab. 93. Orientation change trip angles look-up table .................................................................66 Tab. 94. Resultant trip angle (threshold angle ± hysteresis angle) ............................................. 67 Tab. 95. Orientation change ideal orientation angle definitions ........................................................ 68 Tab. 96. SDCD_INT_SRC1 register (address 2Dh) bit allocation .................................................... 68 Tab. 97. SDCD_INT_SRC1 register (address 2Dh) bit description .................................................. 69 Tab. 98. SDCD_INT_SRC2 register (address 2Eh) bit allocation .................................................... 70 Tab. 99. SDCD_INT_SRC2 register (address 2Eh) bit description .................................................. 70 Tab. 100. SDCD_CONFIG1 register (address 2Fh) bit allocation ......................................................... 71 Tab. 101. SDCD_CONFIG1 register (address 2Fh) bit description ....................................................... 71 Tab. 102. SDCD_CONFIG2 register (address 30h) bit allocation ......................................................... 72 Tab. 103. SDCD_CONFIG2 register (address 30h) bit description ....................................................... 72 Tab. 104. SDCD_OT_DBCNT register (address 31h) bit allocation .................................................... 74 Tab. 105. SDCD_OT_DBCNT register (address 31h) bit description .................................................. 74 Tab. 106. SDCD_WT_DBCNT register (address 32h) bit allocation .................................................... 75 Tab. 107. SDCD_WT_DBCNT register (address 32h) bit description .................................................. 75 Tab. 108. SDCD_LTHS_LSB register (address 33h) bit allocation .................................................... 75 Tab. 109. SDCD_LTHS_LSB register (address 33h) bit description .................................................. 75 Tab. 110. SDCD_LTHS_MSB register (address 34h) bit allocation .................................................... 76 Tab. 111. SDCD_LTHS_MSB register (address 34h) bit description .................................................. 76 Tab. 112. SDCD_UTHS_LSB register (address 35h) bit allocation .................................................... 76 Tab. 113. SDCD_UTHS_LSB register (address 35h) bit description .................................................. 76 Tab. 114. SDCD_UTHS_MSB register (address 36h) bit allocation .................................................... 77 FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 97 / 100 |
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