FXLS8971CF datasheet(55/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

The sleep counter period corresponds to the selected WAKE mode ODR period when operating in LPM and

HPM, and to the effective ODR set by the WAKE decimation (measurement time) and WAKE idle time (off-time)

settings when the device operates in FPM. The auto-WAKE/SLEEP feature is only enabled when the value

written to ASLP_CNT is > 0.

SENS_CONFIG2[WAKE_PM] sets the WAKE power mode; SENS_CONFIG3[WAKE_ODR] sets the ODR.

When operating in Flexible Performance Mode,

SENS_CONFIG3[WAKE_DEC] and WAKE_IDLE[11:0] values

set the effective ODR.

SENS_CONFIG2[SLEEP_PM] sets the SLEEP power mode; SENS_CONFIG3[SLEEP_ODR] sets the ODR.

When operating in Flexible Performance Mode,

SENS_CONFIG3[SLEEP_DEC] and SLEEP_IDLE[11:0] values

set the effective ODR.

The functions used to detect inactivity and enter SLEEP mode upon expiry of the

ASLP_COUNT timer (see

Table 69) are selected in

SENS_CONFIG4 and BUF_CONFIG2. The same functions used to enter SLEEP are

also used to exit this mode when activity is detected except for the SRC_BUF event flag, which can only be

used to prevent/delay a transition from WAKE to SLEEP if the host system is reading data from the buffer (and

clearing SRC_BUF). A transition from SLEEP to WAKE mode occurs as soon as one of the enabled detection

events becomes active. See Table 70 for the corresponding Interrupt event sources.

Bit

Name

ASLP_COUNT[7:0]

Reset

Access

R/W

Table 65. ASLP_COUNT_LSB register (address 1Eh) bit allocation

Field

Description

7 to 0

ASLP_COUNT [7:0]

LSB of the 12-bit unsigned count value used for inactivity detection. The selected WAKE mode

ODR determines the counter period.

Table 66. ASLP_COUNT_LSB register (address 1Eh) bit description

Bit

Name

—

ASLP_COUNT[11:8]

Reset

Access

R/W

Table 67. ASLP_COUNT_MSB register (address 1Fh) bit allocation

Field

Description

3 to 0

ASLP_COUNT [11:8]

MSB (nibble) of the 12-bit unsigned count value used for inactivity detection. The selected WAKE

mode ODR determines the counter period.

Table 68. ASLP_COUNT_MSB register (address 1Fh) bit description

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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