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FXLS8971CF 数据表(PDF) 96 Page - NXP Semiconductors |
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FXLS8971CF 数据表(HTML) 96 Page - NXP Semiconductors |
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96 / 100 page  NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer Tables Tab. 1. Ordering information ..........................................2 Tab. 2. Ordering options ................................................2 Tab. 3. Pin descriptions .................................................4 Tab. 4. Device absolute maximum ratings .................... 6 Tab. 5. ESD and latch-up-protection characteristics ......7 Tab. 6. Nominal operating conditions ............................7 Tab. 7. Accelerometer sensor performance parameters ........................................................ 8 Tab. 8. Electrical characteristics ..................................12 Tab. 9. Temperature sensor performance parameters ...................................................... 14 Tab. 10. I2C serial interface pin description .................. 14 Tab. 11. FXLS8971CF I2C read and write addresses ........................................................15 Tab. 12. I2C secondary timing values for Standard- mode (Sm), Fast-mode (Fm), and Fast- mode Plus (Fm+) ............................................ 15 Tab. 13. Secondary timing values ................................. 21 Tab. 14. Secondary timing values ................................. 22 Tab. 15. FXLS8971CF operating modes descriptions ..................................................... 23 Tab. 16. Operating modes transition criteria ................. 26 Tab. 17. BOOT2 sequence and One-wire motion protocol phase descriptions ............................ 28 Tab. 18. One-wire motion protocol threshold selections .........................................................28 Tab. 19. BOOT1 sequence description (BT_MODE = GND) ............................................................29 Tab. 20. Register address map .....................................30 Tab. 21. INT_STATUS register (address 00h) bit allocation ......................................................... 33 Tab. 22. INT_STATUS register (address 00h) bit description ....................................................... 34 Tab. 23. TEMP_OUT register (address 01h) bit allocation ......................................................... 36 Tab. 24. VECM_LSB register (address 02h) bit allocation ......................................................... 36 Tab. 25. VECM_LSB register (address 02h) bit description ....................................................... 36 Tab. 26. VECM_MSB register (address 03h) bit allocation ......................................................... 36 Tab. 27. VECM_MSB register (address 03h) bit description ....................................................... 37 Tab. 28. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_ CONFIG2[LE_BE] = 0 bit allocation ................ 37 Tab. 29. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_ CONFIG2[LE_BE] = 0 bit allocation ................ 38 Tab. 30. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_ CONFIG2[LE_BE] = 0 bit allocation ................ 38 Tab. 31. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_ CONFIG2[LE_BE] = 1 bit allocation ................ 38 Tab. 32. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_ CONFIG2[LE_BE] = 1 bit allocation ................ 39 Tab. 33. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_ CONFIG2[LE_BE] = 1 bit allocation ................ 39 Tab. 34. BUF_STATUS register (address 0Bh) bit allocation ......................................................... 39 Tab. 35. BUF_STATUS register (address 0Bh) bit description ....................................................... 40 Tab. 36. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_ CONFIG2[LE_BE] = 0 bit allocation ................ 41 Tab. 37. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_ CONFIG2[LE_BE] = 0 bit allocation ................ 41 Tab. 38. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_ CONFIG2[LE_BE] = 0 bit allocation ................ 42 Tab. 39. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_ CONFIG2[LE_BE] = 1 bit allocation ................ 42 Tab. 40. BUF_Y_LSB and BUF_Y_MSB registers (addresses 0Eh, 0Fh) with SENS_ CONFIG2[LE_BE] = 1 bit allocation ................ 42 Tab. 41. BUF_Z_LSB and BUF_Z_MSB registers (addresses 10h, 11h) with SENS_ CONFIG2[LE_BE] = 1 bit allocation ................ 43 Tab. 42. PROD_REV register (address 12h) bit allocation ......................................................... 43 Tab. 43. PROD_REV register (address 12h) bit description ....................................................... 43 Tab. 44. WHO_AM_I register (address 13h) bit allocation ......................................................... 43 Tab. 45. SYS_MODE register (address 14h) bit allocation ......................................................... 44 Tab. 46. SYS_MODE register (address 14h) bit description ....................................................... 44 Tab. 47. SENS_CONFIG1 register (address 15h) bit allocation ......................................................... 45 Tab. 48. SENS_CONFIG1 register (address 15h) bit description ....................................................... 45 Tab. 49. SENS_CONFIG2 register (address 16h) bit allocation ......................................................... 46 Tab. 50. SENS_CONFIG2 register (address 16h) bit description ....................................................... 47 Tab. 51. SENS_CONFIG3 register (address 17h) bit allocation ......................................................... 48 Tab. 52. WAKE and SLEEP low-power mode ODR and decimation settings .................................. 48 Tab. 53. WAKE and SLEEP High Performance mode ODR and decimation settings ................49 Tab. 54. WAKE and SLEEP decimation settings in Flexible Power mode ...................................... 50 Tab. 55. SENS_CONFIG4 register (address 18h) bit allocation ......................................................... 50 FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 96 / 100 |
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